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9ZXL1530 Folha de dados(PDF) 6 Page - Integrated Device Technology |
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9ZXL1530 Folha de dados(HTML) 6 Page - Integrated Device Technology |
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6 / 19 page  9ZXL1530 15-OUTPUT LOW POWER DIFFERENTIAL ZBUFFER FOR PCIE GEN3 AND QPI IDT® 15-OUTPUT LOW POWER DIFFERENTIAL ZBUFFER FOR PCIE GEN3 AND QPI 6 9ZXL1530 REV C 031312 Electrical Characteristics–Input/Supply/Common Output Parameters TA = TCOM; Supply Voltage VDD/VD DA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS N OTES Ambient Operating Temperature T COM C ommmercial range 0 70 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus, low threshold and tri-level inputs 2 VDD + 0.3 V1 Input Low Voltage VIL Single-ended inputs, except SMBus, low threshold and tri-level inputs GND - 0.3 0.8 V 1 IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1 I IN P Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 F ibyp V DD = 3. 3 V, Bypass mod e 33 150 MHz 2 Fip ll VDD = 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2 F ip ll V DD = 3.3 V, 1 33.33 MHz PL L m ode 120 133.33 147 MHz 2 Pin Inductance L pin 7nH 1 CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 C IN DIF _IN DIF_IN differential clock inputs 1.5 2.7 pF 1,4 C OUT Output pin capacitance 6 pF 1 C lk Stabilization T STAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1ms 1,2 Input SS Modulation Frequency f MOD IN Allowable Frequency (Triangular Modulation) 30 33 kHz 1 Tdrive_PD# t DRVPD DIF output enable after PD# de-assertion 300 us 1,3 Tfall tF Fall time of control inputs 5 ns 1,2 Trise t R R ise time of control inputs 5 ns 1,2 SMBus Input Low Voltage V IL SMB 0.8 V 1 SMBus Input High Voltage VIHSM B 2.1 VDDSMB V1 SMBus Output Low Voltage V OL SMB @ I PU LLU P 0.4 V 1 SMBus Sink Current IPUL LUP @ VOL 4mA 1 Nominal Bus Voltage VDDSMB 3V to 5V +/- 10% 2.7 5.5 V 1 SCLK/SD ATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time t FSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMINSM B Minimum SMBus operating frequency 100 kHz 1,5 1 Guaranteed by design and characterization, not 100% tested in production. 2Control input must be monotonic from 20% to 80% of input swing. 5The differential input clock must be running for the SMBus to be active Input Current 3Time from deassertion until outputs are >200 mV 4DIF_IN input Capacitance Input Frequency |
Nº de peça semelhante - 9ZXL1530 |
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Descrição semelhante - 9ZXL1530 |
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