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TPA3140D2 Folha de dados(PDF) 4 Page - Texas Instruments |
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TPA3140D2 Folha de dados(HTML) 4 Page - Texas Instruments |
4 / 40 page TPA3140D2 SLOS882A – JANUARY 2015 – REVISED APRIL 2015 www.ti.com Pin Functions PIN I/O/P(1) DESCRIPTION NAME NUMBER Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels SD 1 I with compliance to AVCC. Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. FAULT 2 O Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC. LINP 3 I Positive audio input for left channel. Biased at 3V. Connect to GND for PBTL mode. LINN 4 I Negative audio input for left channel. Biased at 3V. Connect to GND for PBTL mode. Decay speed for clip free power limiter. Connect a resistor divider from GVDD to GND to set decay LIMRATE 5 I speed. Connect directly to GND to disconnect limiter. GAIN 6 I 4-state Amplifier gain select. Connect a resistor divider from GVDD to GND to set closed loop gain. Spread spectrum control. Connect a resistor divider from GVDD to GND to set mode. Connect to GND SSCTRL 7 I for disable spread spectrum. LIMTHR Voltage limit level for AGL and power limiter. Connect a resistor divider from GVDD to GND to set limit. 8 I ES Connect directly to GVDD to disconnect limiter High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as supply for LIMTHRES GVDD 9 O limit function GND 10 P Analog signal ground. RINN 11 I Negative audio input for right channel. Biased at 3V. RINP 12 I Positive audio input for right channel. Biased at 3V. 1SPW 13 I Modulation scheme select. Low: BD mode, high: 1SPW mode. AVCC 14 P Analog supply Power supply for right channel H-bridge. Right channel and left channel power supply inputs are PVCC 15 P connected internally. Power supply for right channel H-bridge. Right channel and left channel power supply inputs are PVCC 16 P connected internally. BSPR 17 I Bootstrap I/O for right channel, positive high-side FET. OUTPR 18 O Class-D H-bridge positive output for right channel. GND 19 P Power ground for the H-bridges. OUTNR 20 O Class-D H-bridge negative output for right channel. BSNR 21 I Bootstrap I/O for right channel, negative high-side FET. BSNL 22 I Bootstrap I/O for left channel, negative high-side FET. OUTNL 23 O Class-D H-bridge negative output for left channel. GND 24 P Power ground for the H-bridges. OUTPL 25 O Class-D H-bridge positive output for left channel. BSPL 26 I Bootstrap I/O for left channel, positive high-side FET. Power supply for left channel H-bridge. Right channel and left channel power supply inputs are PVCC 27 P connected internally. Power supply for left channel H-bridge. Right channel and left channel power supply inputs are PVCC 28 P connected internally. Thermal Pad P Connect to GND for best thermal and electrical performance (1) I = Input, O = Output, P = Power 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPA3140D2 |
Nº de peça semelhante - TPA3140D2_15 |
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Descrição semelhante - TPA3140D2_15 |
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