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TS3A5017 Folha de dados(PDF) 5 Page - Texas Instruments |
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TS3A5017 Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 37 page TS3A5017 www.ti.com SCDS188E – JANUARY 2005 – REVISED APRIL 2015 6.5 Electrical Characteristics for 3.3-V Supply V+ = 2.7 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT Analog Switch Analog signal VD, VS 0 V+ V range 25°C 11 12 ON-state 0 ≤ VS ≤ V+, Switch ON, ron 3 V Ω resistance ID = –32 mA, see Figure 12 Full 14 ON-state 25°C 1 2 resistance VS = 2.1 V, Switch ON, Δron match 3 V Ω ID = –32 mA, see Figure 12 Full 3 between channels ON-state 25°C 7 9 0 ≤ VS ≤ V+, Switch ON, ron(flat) resistance 3 V Ω ID = –32 mA, see Figure 12 Full 10 flatness VS = 1 V, VD = 3 V, 25°C –0.1 0.05 0.1 IS(OFF) or 3.6 V S Full –0.2 0.2 Switch OFF, VS = 3 V, VD = 1 V, OFF leakage μA see Figure 13 current 25°C –1 0.5 1 VS = 0 to 3.6 V, ISPWR(OFF) 0 V VD = 3.6 V to 0, Full –5 5 VS = 1 V, VD = 3 V, 25°C –0.1 0.05 0.1 ID(OFF) or 3.6 V D Full –0.2 0.2 Switch OFF, VS = 3 V, VD = 1 V, OFF leakage μA see Figure 13 current 25°C –1 0.5 1 VD = 0 to 3.6 V, IDPWR(OFF) 0 V VS = 3.6 V to 0, Full –5 5 S VS = 1 V, VD = Open, 25°C –0.1 0.05 0.1 Switch ON, IS(ON) ON leakage or 3.6 V μA see Figure 14 Full –0.2 0.2 current VS = 3 V, VD = Open, D VD = 1 V, VS = Open, 25°C –0.1 0.05 0.1 Switch ON, ID(ON) ON leakage or 3.6 V μA see Figure 14 Full –0.2 0.2 current VD = 3 V, VS = Open, Digital Control Inputs (IN1, IN2, EN)(2) VIH Input logic high Full 2 V+ V VIL Input logic low Full 0 0.8 V 25°C –1 0.05 1 Input leakage IIH, IIL VI = V+ or 0 3.6 V μA current Full –1 1 VGEN = 0, RGEN = 0, QC Charge injection See Figure 21 25°C 3.3 V 5 pC CL = 0.1 nF, S VS = V+ or GND, CS(OFF) OFF See Figure 15 25°C 3.3 V 4.5 pF Switch OFF, capacitance D VD = V+ or GND, CD(OFF) OFF See Figure 15 25°C 3.3 V 19 pF Switch OFF, capacitance S VS = V+ or GND, CS(ON) See Figure 15 25°C 3.3 V 25 pF ON capacitance Switch ON, D VD = V+ or GND, CD(ON) See Figure 15 25°C 3.3 V 25 pF ON capacitance Switch ON, Digital input CI VI = V+ or GND, See Figure 15 25°C 3.3 V 2 pF capacitance RL = 50 Ω, BW Bandwidth See Figure 17 25°C 3.3 V 165 MHz Switch ON, RL = 50 Ω, OISO OFF isolation See Figure 18 25°C 3.3 V –48 dB f = 1 MHz, (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TS3A5017 |
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