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ISLA118P50IRZ Folha de dados(PDF) 7 Page - Intersil Corporation |
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ISLA118P50IRZ Folha de dados(HTML) 7 Page - Intersil Corporation |
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7 / 34 page  ISLA118P50 7 FN7565.2 July 25, 2011 Spurious-Free Dynamic Range (Notes 11, 12) SFDR fIN = 10MHz 68 dBc fIN = 105MHz 63.5 68 dBc fIN = 190MHz 68 dBc fIN = 364MHz 67 dBc fIN = 495MHz 67 dBc fIN = 605MHz 63 dBc fIN = 995MHz 48 dBc Intermodulation Distortion IMD fIN = 70MHz 80 dBc fIN = 170MHz 80 dBc Word Error Rate WER 10-12 Full Power Bandwidth FPBW 1.15 GHz I2E SPECIFICATIONS Offset mismatch-induced spurious power No I2E Calibration performed -70 dBFS Active Run state enabled -81 dBFS I2E Settling Times I2Epost_t Calibration settling time for Active Run state 1000 ms Minimum Duration of Valid Analog Input (Note 13) tTE Allow one I2E iteration of Offset, Gain and Phase correction 500 µs Largest Interleave Spur fIN = 10MHz to 240MHz, Active Run State enabled, in Track Mode -94 dBc fIN = 10MHz to 240MHz, Active Run State enabled and previously settled, in Hold Mode -82 dBc fIN = 260MHz to 490MHz, Active Run State enabled, in Track Mode -89 dBc fIN = 260MHz to 490MHz, Active Run State enabled and previously settled, in Hold Mode -79 dBc Total Interleave Spurious Power Active Run State enabled, in Track Mode, fIN is a broadband signal in the 1st Nyquist zone -90 dBc Active Run State enabled, in Track Mode, fIN is a broadband signal in the 2nd Nyquist zone -85 dBc Sample Time Mismatch Between Unit A/Ds Active Run State enabled, in Track Mode 30 fs Gain Mismatch Between Unit A/Ds 0.01 % Offset Mismatch Between Unit A/Ds 1mV NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 8. See “Nap/Sleep” for more detail. 9. AC Specifications apply after internal calibration of the A/D is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” and “User Initiated Reset” for more detail. 10. The DLL Range setting must be changed for low speed operation. 11. The offset mismatch-induced spur energy, which occurs at fSAMPLE/2, is not included in any specification unless otherwise noted. 12. This specification only applies when I2E is in Active Run state, and in Track Mode. 13. Limits are specified over the full operating temperature and voltage range and are established by characterization and not production tested. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, FIN =105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. (Continued) PARAMETER SYMBOL CONDITIONS ISLA118P50 (Note 6) UNITS MIN TYP MAX |
Nº de peça semelhante - ISLA118P50IRZ |
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Descrição semelhante - ISLA118P50IRZ |
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