Os motores de busca de Datasheet de Componentes eletrônicos |
|
ML2252CCQ Folha de dados(PDF) 5 Page - Micro Linear Corporation |
|
ML2252CCQ Folha de dados(HTML) 5 Page - Micro Linear Corporation |
5 / 13 page ML2252, ML2259 5 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC and Dynamic Performance Characteristics (Note 5) tACQ Sample and Hold Acquisition 1/2 1/fCLK fCLK Clock Frequency 10 1460 kHz tC Conversion Time 8.5 8.5 + 250ns 1/fCLK SNR Signal to Noise Ratio VIN = 51kHz, 5V sine. 47 dB fCLK = 1.46MHz (fSAMPLING > 150kHz). Noise is sum of all nonfundamental components up to 1/2 of fSAMPLING THD Total Harmonic Distortion VIN = 51kHz, 5V sine. –60 dB fCLK = 1.46MHz (fSAMPLING > 150kHz). THD is sum 2, 3, 4, 5 harmonics relative to fundamental IMD Intermodulation Distortion VIN = fA + fB. fA = 49kHz, 2.5V sine. –60 dB fB = 47.8kHz, 2.5V sine, fCLK = 1.46MHz (fSAMPLING > 150kHz). IMD is (fA + fB), (fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB), (fA – 2fB) relative to fundamental FR Frequency Response VIN = 0 to 50kHz. 5V sine relative 0.1 dB to 1kHz tDC Clock Duty Cycle (Note 6) 40 60 % tEOC End of Conversion Delay 1/2 1/2 + 250ns 1/fCLK tWS Start Pulse Width 50 ns tSS Start Pulse Setup Time Synchronous only, (Note 7) 40 ns tWALE Address Latch Enable 50 ns Pulse Width tS Address Setup 0 ns tH Address Hold 50 ns tH1, H0 Output Enable for DB0–DB7 Figure 1, CL = 50pF 100 ns Figure 1, CL = 10pF 50 ns t1H, 0H Output Disable for DB0–DB7 Figure 1, CL = 50pF 100 ns Figure 1, CL = 10pF 50 ns CIN Capacitance of Logic Input 5 pF COUT Capacitance of Logic Outputs 10 pF Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors. Note 3: For –VREF • VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading. Note 4: Leakage current is measured with the clock not switching. Note 5: CL = 50pF, timing measured at 50% point. Note 6: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs. Note 7: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met, start conversion will have an uncertainty of one clock pulse. |
Nº de peça semelhante - ML2252CCQ |
|
Descrição semelhante - ML2252CCQ |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |