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LMZ36002 Folha de dados(PDF) 3 Page - Texas Instruments

Nome de Peças LMZ36002
Descrição Electrónicos  SIMPLE SWITCHER 4.5-V to 60-V Input, 2-A Power Module
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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LMZ36002 Folha de dados(HTML) 3 Page - Texas Instruments

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LMZ36002
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SNVSA92A – SEPTEMBER 2015 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
RVQ Package
43-Pin QFN
(Top View)
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
Zero volt reference for the analog control circuitry. All of these pins are not connected together
1, 2, 3, 4,
internal to the device and must be connected to one another externally using an analog ground plane
AGND
G
5, 11, 12
on the PCB. Pins 11 and 12 are internally connected to the PGND of the device at a single point. The
analog ground plane of the PCB should allow only analog ground currents to flow through these pins.
Synchronization input to synchronize the device to an external clock. Connect this pin to AGND if not
CLK
8
I
used.
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage.
DNC
6, 40
-
These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
Inhibit and UVLO adjust pin. Use an open drain or open collector device to control the inhibit function.
INH/UVLO
26
I
A resistor divider between this pin, AGND, and PVIN adjusts the UVLO voltage. Connect this pin to
PVIN if not used.
This is the return current path for the power stage of the device. Connect these pins to the input
19, 29, 30,
source, the load, and to the bypass capacitors associated with PVIN and VOUT using power ground
PGND
31, 32, 33,
G
planes on the PCB. Pad 41 should be connected to the ground planes using multiple vias for good
41
thermal performance.
34, 35, 36,
Phase switch node. Do not place any external components on these pins or tie them to a pin of
PH
O
37, 38, 39
another function.
Power input voltage. These pins supply all of the power to the device. Connect these pins to the input
PVIN
27, 28, 42
I
source and connect external bypass capacitors between these pins and PGND close to the device.
Power Good flag pin. This open drain output asserts low if the output voltage is more than
PWRGD
20
O
approximately ±10% out of regulation. This pin is internally connected to an uncommitted 100k pull-
up resistor that can be pulled up to a user-defined voltage applied to the PWRGD_PU pin.
An internal 100 k pull-up resistor is connected between this pin and the PWRGD pin. If use of this
PWRGD_P
21
I
internal pull-up resistor is desired, connect this pin to an appropriate voltage source that is less than
U
or equal to 12 V. If unused, leave this pin floating.
This pin is connected to internal frequency setting circuitry which sets the default switching frequency
RT
9
I
to 500 kHz. An external resistor can be connected from this pin to AGND to adjust the switching
frequency. Refer to application section in datasheet.
(1)
G = Ground, I = Input, O = Output
Copyright © 2015, Texas Instruments Incorporated
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