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54ACT283D Folha de dados(PDF) 2 Page - National Semiconductor (TI) |
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54ACT283D Folha de dados(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Functional Description (Continued) Note that as long as A 2 and B2 are the same, whether HIGH or LOW, they do not influence S 2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S 0,S1 and S2 present a bi- nary number equal to the number of inputs I 1–I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I 1–I5 are true, the output M 5 is true. C 0 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 S 0 S 1 S 2 S 3 C 4 Logic Levels L L H L H H L L H H H L L H Active HIGH 00101100111001 Active LOW 11010011000110 Active HIGH:0+10+9 = 3 + 16 Active LOW:1+5+6 = 12+0 FIGURE 1. Active HIGH versus Active LOW Interpretation DS100977-5 FIGURE 2. 3-Bit Adder DS100977-6 FIGURE 3. 2-Bit and 1-Bit Adders DS100977-7 FIGURE 4. 5-Input Encoder DS100977-8 FIGURE 5. 5-Input Majority Gate www.national.com 2 |
Nº de peça semelhante - 54ACT283D |
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Descrição semelhante - 54ACT283D |
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