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TS1102-200EG5 Folha de dados(PDF) 4 Page - Silicon Laboratories |
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TS1102-200EG5 Folha de dados(HTML) 4 Page - Silicon Laboratories |
4 / 20 page 2.2 Theory of Operation The internal configuration of the TS1100/02 (a unidirectional high-side, current-sense amplifier) is based on a common operational am- plifier circuit used for measuring load currents (in one direction) in the presence of high common-mode voltages. In the general case, a current-sense amplifier monitors the voltage caused by a load current through an external sense resistor and generates an output volt- age as a function of that load current. The internal configuration of the TS1101/03 (a bidirectional high-side, current-sense amplifier) is a variation of the TS1100/02 unidirec- tional current-sense amplifier. In the design of the TS1101/03, the input amplifier was reconfigured for fully differential input/output oper- ation and a second low-threshold p-channel FET (M2) was added where the drain terminal of M2 is also connected to ROUT. Therefore, the behavior of the TS1101/03 for when VRS– > VRS+ is identical for when VRS+ > VRS–. Referring to the typical application circuit, the inputs of the op-amp based circuit are connected across an external RSENSE resistor that is used to measure load current. At the non-inverting input of the current-sense amplifier (the RS+ terminal), the applied voltage is ILOAD × RSENSE. Since the RS– terminal is the non-inverting input of the internal op-amp, op-amp feedback action forces the inverting input of the internal op-amp to the same potential. Therefore, the voltage drop across RSENSE (VSENSE) and the voltage drop across RGAINA (at the RS+ terminal) are equal. Necessary for gain ratio matched, both RGAINA and RGAINB are the same value. Since p-channel M1’s source is connected to the inverting input of the internal op amp and since the voltage drop across RGAINA is the same as the external VSENSE, op amp feedback action drives the gate of M1 such that M1’s drain-source current is equal to: IDS(M 1) = VSENSE RGAINA or IDS(M 1) = ILOAD × RSENSE RGAINA Since M1’s drain terminal is connected to ROUT, the output voltage of the current-sense amplifier at the OUT terminal is, therefore: VOUT = ILOAD × RSENSE × ROUT RGAINA For the TS1101 and TS1103, when the voltage at the RS– terminal is greater than the voltage at the RS+ terminal, the external VSENSE voltage drop is impressed upon RGAINB. The voltage drop across RGAINB is then converted into a current by M2 that then produces an output voltage across ROUT. In this design, when M1 is conducting current (VRS+ > VRS–), the TS1101/03’s internal amplifi- er holds M2 OFF. When M2 is conducting current (VRS– > VRS+), the internal amplifier holds M1 OFF. In either case, the disabled FET does not contribute to the resultant output voltage. The current-sense amplifier’s gain accuracy is therefore the ratio match of ROUT to RGAIN[A/B]. For each of the four gain options availa- ble, Table 1 lists the values for ROUT and RGAIN[A/B]. The TS1101’s output stage is protected against input overdrive by use of an output current-limiting circuit of 3 mA (typical) and a 7 V internal clamp protection circuit. TS1100/01/02/03 Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 3 |
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