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CD4034BC Folha de dados(PDF) 1 Page - National Semiconductor (TI) |
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CD4034BC Folha de dados(HTML) 1 Page - National Semiconductor (TI) |
1 / 12 page TLF5963 February 1988 CD4034BMCD4034BC 8-Stage TRI-STATE Bidirectional ParallelSerial InputOutput Bus Register General Description The CD4034BMCD4034BC is an 8-bit CMOS static shift register with two parallel bidirectional data ports (A and B) which when combined with serial shifting operations can be used to (1) bidirectionally transfer parallel data between two buses (2) convert serial data to parallel form and direct them to either of two buses (3) store (recirculate) parallel data or (4) accept parallel data from either of two buses and convert them to serial form These operations are con- trolled by five control inputs A ENABLE (AE) ‘‘A’’ data port is enabled only when AE is at logical ‘‘1’’ This allows the use of a common bus for multiple packages A-BUS-TO-B-BUSB-BUS-TO-A-BUS (AB) This input controls the direction of data flow When at logical ‘’1’’ data flows from port A to B (A is input B is output) When at logical ‘‘0’’ the data flow direction is reversed ASYNCHRONOUSSYNCHRONOUS (AS) When AS is at logical ‘‘0’’ data transfer occurs at positive tran- sition of the CLOCK When AS is at logical ‘‘1’’ data transfer is independent of the CLOCK for parallel opera- tion In serial mode AS input is internally disabled such that operation is always synchronous (Asynchronous serial operation is not possible) PARALLELSERIAL (PS) A logical ‘‘1’’ PS input al- lows data transfer into the registers via A or B port (syn- chronous if AS e logical ‘‘0’’ asynchronous if AS e logical ‘‘1’’) A logical ‘‘0’’ PS allows serial data to transfer into the register synchronously with the positive transition of the CLOCK independent of the AS input CLOCK Single phase enabled only in synchronous mode (Either PS e logical ‘‘1’’ and AS e logical ‘‘0’’ or PS e logical ‘‘0’’ All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave All inputs are protected against damage due to static dis- charge by diode clamps to VDD and VSS Features Y Wide supply voltage range 30V to 18V Y High noise immunity 045 VDD (typ) Y Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Y RCA CD4034B second source Applications Y Parallel InputParallel Output Parallel InputSerial Output Serial InputParallel Output Serial InputSerial Output register Y Shift rightshift left register Y Shift rightshift left with parallel loading Y Address register Y Buffer register Y Bus system register with enable parallel lines at bus side Y Double bus register system Y Up-down Johnson or ring counter Y Pseudo-random code generators Y Sample and hold register (storage counting display) Y Frequency and phase comparator Connection Diagram Dual-In-Line Package TLF5963 – 1 Top View Order Number CD4034B TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
Nº de peça semelhante - CD4034BC |
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Descrição semelhante - CD4034BC |
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