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LM25122QPWPRQ1 Folha de dados(PDF) 3 Page - Texas Instruments |
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LM25122QPWPRQ1 Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 47 page VCC UVLO CSP OPT CSN VIN SLOPE SYNCIN/RT BST COMP RES SW LO HO AGND SS PGND 1 6 2 3 4 5 8 9 20 14 15 19 18 17 16 13 12 11 EP MODE 10 7 FB SYNCOUT LM25122-Q1 www.ti.com SNVSAF0A – DECEMBER 2015 – REVISED DECEMBER 2015 5 Pin Configuration and Functions PWP Package 20-Pin HTSSOP With Exposed Pad Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. AGND 9 G Analog ground connection. Return for the internal voltage reference and analog circuits. High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high- BST 20 P side N-channel MOSFET gate and should be placed as close to controller as possible. An internal BST charge pump will supply 200-µA current into bootstrap capacitor for bypass operation. Output of the internal error amplifier. The loop compensation network should be connected between COMP 11 O this pin and the FB pin. CSN 3 I Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor. Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense CSP 4 I resistor. Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin FB 10 I sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. The controller is configured as slave mode if the FB pin voltage is above 2.7 V at initial power-on. High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous HO 19 O N-channel MOSFET switch through a short, low inductance path. Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel LO 16 O MOSFET switch through a short, low inductance path. Switching mode selection pin. 700-k Ω pullup and 100-kΩ pulldown resistor internal hold MODE pin to 0.15 V as a default. By adding external pullup or pulldown resistor, MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2 V diode emulation mode threshold, forced PWM mode is enabled, allowing current to flow in either direction through the high-side N- MODE 13 I channel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode. Skip cycle comparator is activated as a default. If MODE pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load. Clock synchronization selection pin. This pin also enables/disables SYNCOUT related with OPT 2 I master/slave configuration. The OPT pin should not be left floating. Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the PGND 15 G source terminal of the low-side N-channel MOSFET switch. The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay RES 14 O during over load conditions. Connect directly to the AGND when hiccup mode operation is not required. (1) G = Ground, I = Input, O = Output, P = Power Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM25122-Q1 |
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