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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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LM2502 Folha de dados(PDF) 8 Page - Texas Instruments |
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LM2502 Folha de dados(HTML) 8 Page - Texas Instruments |
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8 / 31 page  LM2502 SNLS176L – JANUARY 2004 – REVISED MAY 2013 www.ti.com SWITCHING CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units PARALLEL BUS TIMING tSET Set Up Time, Data to Edge Inputs 5 ns tHOLD Hold Time, Edge to Data 5 ns tRISE Rise Time See Figure 2, VDDIO = 1.7V 2 7 14 ns Outputs, VDDIO = 3.3V 1 2 10 ns CL = 10 pF tFALL Fall Time VDDIO = 1.7V 2 6 14 ns Edge sensitive outputs tested only: VDDIO = 3.3V m68 mode: CS1*, CS2* and CLKout 1 2 10 ns i80 mode: RD*, WR*, and CLKout CLKDC Output Clock Duty Cycle CLKDIS* = H, Slave (DES) 50 % Parallel Bus Timing - See Figure 13 Figure 14 Figure 15 Figure 16 and Table 7, Table 8, Table 9, and Table 10 SERIAL BUS TIMING tDVBC Data Valid before Clock Master-to-Slave (2) 2.0 ns tDVAC Data Valid after Clock 0.5 ns POWER UP TIMING(2) t0 Master PLL Lock Counter See Figure 6 CLK 4096 cycles t1 MC Pulse Width Low (Master) CLK 11 cycles t2 MC Pulse Width HIGH CLK 11 (Master) cycles t3 MC Pulse Width Low (Master) CLK 11 cycles t4 CLK-Out Delay (Slave) MC 7 cycles t5 Power Up Total delay CLK 4133 (t0 + t1 + t2 + t3 + t4) cycles MPL POWER OFF TIMING tPAZ Disable Time to Power Down See Figure 7, This parameter is functionally tested by the IDDZ parameter. 50 ms (3) (1) Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25°C. (2) This parameter is specified by design based on simulation or bench characterization. (3) This parameter is specified by a ATE tester delay, actual turn off time is faster. RECOMMENDED INPUT TIMING REQUIREMENTS Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units MASTER REFERENCE CLOCK (CLK) fCLK Clock Frequency See Table 12(2) 3 26 MHz tCP Clock Period 38.5 333 ns CLKDC Clock Duty Cycle 40 50 60 % tT Clock Transition Times (Rise 1 14 ns or Fall, 20%–80%) (1) Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25°C. (2) This parameter is specified by design based on simulation or bench characterization. 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM2502 |
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