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TMP175AIDR Folha de dados(PDF) 9 Page - Texas Instruments |
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TMP175AIDR Folha de dados(HTML) 9 Page - Texas Instruments |
9 / 13 page TMP175, 75 SBOS288C www.ti.com 9 GENERAL CALL The TMP175 and TMP75 respond to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device will acknowledge the General Call address and respond to com- mands in the second byte. If the second byte is 00000100, the TMP175 and TMP75 will latch the status of their address pins, but will not reset. If the second byte is 00000110, the TMP175 and TMP75 will latch the status of their address pins and reset their internal registers to their power-up values. HIGH-SPEED MODE In order for the Two-Wire bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP175 and TMP75 will not acknowledge this byte, but will switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master will transmit a Two-Wire slave address to initiate a data transfer operation. The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP175 and TMP75 will switch the input and output filter back to fast-mode operation. TIMEOUT FUNCTION The TMP175 and TMP75 will reset the serial interface if either SCL or SDA are held low for 54ms (typ) between a START and STOP condition. The TMP175 and TMP75 will release the bus if it is pulled low and will wait for a start condition. The timeout function requires a communication speed of at least 1kHz for SCL operating frequency. TIMING DIAGRAMS The TMP175 and TMP75 are Two-Wire and SMBus compat- ible. Figures 4 to 8 describe the various operations on the TMP175 and TMP75. Bus definitions are given below. Pa- rameters for Figure 4 are defined in Table XIII. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred be- tween a START and a STOP condition is not limited and is determined by the master device. The receiver acknowl- edges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into ac- count. On a master receive, the termination of the data transfer can be signaled by the master generating a Not- Acknowledge on the last byte that has been transmitted by the slave. FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNITS SCL Operating Frequency f(SCL) 0.001 0.4 0.001 3.4 MHz Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns Hold Time After Repeated START Condition. t(HDSTA) 100 100 ns After this period, the first clock is generated. Repeated START Condition Setup Time t(SUSTA) 100 100 ns STOP Condition Setup Time t(SUSTO) 100 100 ns Data Hold Time t(HDDAT) 00 ns Data Setup Time t(SUDAT) 100 10 ns SCL Clock LOW Period t(LOW) 1300 160 ns SCL Clock HIGH Period t(HIGH) 600 60 ns Clock/Data Fall Time tF 300 160 ns Clock/Data Rise Time tR 300 160 ns TABLE XIII. Timing Diagram Definitions for TMP175 and TMP75. |
Nº de peça semelhante - TMP175AIDR |
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Descrição semelhante - TMP175AIDR |
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