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SN74AHC594NSRE4 Folha de dados(PDF) 6 Page - Texas Instruments |
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SN74AHC594NSRE4 Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 27 page SN54AHC594, SN74AHC594 SCLS423G – JUNE 1998 – REVISED JULY 2014 www.ti.com 6.6 Timing Requirements, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) TA = 25°C SN54AHC594(1) SN74AHC594 UNIT MIN MAX MIN MAX MIN MAX RCLK or SRCLK high or low 5.5 5.5 5.5 tw Pulse Duration ns RCLR or SRCLR low 5 5 5 SER before SRCLK ↑ 3.5 3.5 3.5 SRCLK ↑ before RCLK↑(2) 8 8.5 8.5 tsu Setup time SRCLR low before SRCLK ↑ 8 9 9 ns SRCLR high (inactive) before SRCLK ↑ 4.2 4.8 4.8 RCLR high (inactive) before RCLK ↑ 4.6 5.3 5.3 Hold time, th SER after SRCLK ↑ 1.5 1.5 1.5 ns data after CLK ↑ (1) Product Preview (2) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. 6.7 Timing Requirements, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) TA = 25°C SN54AHC594(1) SN74AHC594 UNIT MIN MAX MIN MAX MIN MAX RCLK or SRCLK high or low 5 5 5 tw Pulse Duration ns RCLR or SRCLR low 5.2 5.2 5.2 SER before SRCLK ↑ 3 3 3 SRCLK ↑ before RCLK↑(2) 5 5 5 tsu Setup time SRCLR low before SRCLK ↑ 5 5 5 ns SRCLR high (inactive) before SRCLK ↑ 2.9 3.3 3.3 RCLR high (inactive) before RCLK ↑ 3.2 3.7 3.7 Hold time, th SER after SRCLK ↑ 2 2 2 ns data after CLK ↑ (1) Product Preview (2) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. 6 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC594 SN74AHC594 |
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