14 15

RESET

DTRB

DTRA

RTSA

OPA

RXRDYA

INTA

INTB

A0

A1

A2

NC

36

35

34

33

32

31

30

29

28

27

26

25

16

1

2

3

4

5

6

7

8

9

10

1 1

12

D5

D6

D7

RXB

RXA

TXRDYB

TXA

TXB

OPB

CSA

CSB

NC

17 18 19 20

PFB PACKAGE

(TOP VIEW)

47 46 45 44 43

48

42

40 39 38

41

21 22 23 24

37

13

TL16C2550PFB

TL16C2550-Q1

SLWS232

– DECEMBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the

TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode),

each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by

buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their

respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO

mode, a selectable autoflow control feature can significantly reduce software overload and increase system

efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input,

thus eliminating overruns in the receive FIFO.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and

stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on

data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status

of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt

system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors from

1 to 65535, thus producing a 16

× internal reference clock for the transmitter and receiver logic. Each ACE

accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would

generate a 667-ns bit time and a 6.7-

µs character time (for 8,N,1 serial data), with the internal clock running at

24 MHz.

Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.

NC - No internal connection

2

Submit Documentation Feedback

Copyright

© 2011, Texas Instruments Incorporated

Product Folder Link(s) :TL16C2550-Q1