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TL16C2550IPFBRQ1 Folha de dados(PDF) 11 Page - Texas Instruments |
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TL16C2550IPFBRQ1 Folha de dados(HTML) 11 Page - Texas Instruments |
11 / 38 page TL16C2550-Q1 www.ti.com SLWS232 – DECEMBER 2011 ELECTRICAL CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT 5 V NOMINAL High-level output VOH IOH = –4 mA 4 V voltage(2) VOL Low-level output voltage(2) IOL = 4 mA 0.4 V II Input current VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, All other terminals floating 10 µA High-impedance-state VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, Chip slected in write mode IOZ ±20 µA output current or chip deselcted VCC = 5.5 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB, ICC Supply current CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, 7.5 mA XTAL1 at 24 MHz, No load on outputs Ci(CLK) Clock input impedance(3) 15 20 pF CO(CLK) Clock output impedance(3) 20 30 pF VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals grounded CI Input impedance(3) 6 10 pF CO Output impedance(3) 10 20 pF (1) All typical values are at VCC = 5 V and TA = 25°C. (2) These parameters apply for all outputs except XTAL2. (3) Not production tested. TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 1.8 V 2.5 V 3.3 V 5 V ALT. TEST PARAMETER FIGURE UNIT SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX tw8 Pulse duration, RESET tRESET 1 1 1 1 µs tw1 Pulse duration, clock high tXH 6 40 25 20 18 ns tw2 Pulse duration, clock low tXL 8 115 80 62 57 ns tcR Cycle time, read (tw7 + td8 + th7) RC 8 115 80 62 57 ns tcW Cycle time, write (tw6 + td5 + th4) WC 7 115 80 62 57 ns tw6 Pulse duration, IOW tIOW 7 80 55 45 40 ns tw7 Pulse duration, IOR tIOR 8 80 55 45 40 ns tSU3 Setup time, data valid before IOW ↑ tDS 7 25 20 15 15 ns th3 Hold time, CS valid after IOW ↑ tWCS 7 0 0 0 0 ns th4 Hold time, address valid after IOW ↑ tWA 7 20 15 10 10 ns th5 Hold time, data valid after IOW ↑ tDH 7 15 10 5 5 ns th6 Hold time, chip select valid after IOR ↑ tRCS 8 0 0 0 0 ns th7 Hold time, address valid after IOR ↑ tRA 8 20 15 10 10 ns td4 Delay time, CS valid before IOW ↓ tCSW 7 0 0 0 0 ns td5 Delay time, address valid before IOW ↓ tAW 7 15 10 7 7 ns td7 Delay time, CS valid to IOR ↓ tCSR 8 0 0 0 0 ns td8 Delay time, address valid to IOR ↓ tAR 8 15 10 7 7 ns td10 Delay time, IOR ↓ to data valid tRVD 8 CL = 30 pF 55 35 25 20 ns td11 Delay time, IOR ↓ to floating data tHZ 8 CL = 30 pF 40 30 20 20 ns Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :TL16C2550-Q1 |
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