DESCRIPTION

TL16C2752

The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software

compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional

functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are

larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls,

software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit

threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.

The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the

functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs.

The two UARTs share only the data bus interface and clock source, otherwise they operate independently.

Another name for the UART function is asynchronous communications element (ACE), and these terms will be

used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding

that two such devices are incorporated into the TL16C2752.

Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE

can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering

received and to-be-transmitted characters. Each receiver and transmitter store up to 64 bytes in their respective

FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode,

selectable hardware or software autoflow control features can significantly reduce program overload and

increase system efficiency by automatically controlling serial data flow.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and

stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on

data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status

of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt

system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of

from 1 to 65535, thus producing a 16× or 8× internal reference clock for the transmitter and receiver logic. Each

ACE accommodates up to a 3-Mbaud serial data rate (48-MHz input clock). As a reference point, that speed

would generate a 333-ns bit time and a 3.33-

＝s character time (for 8,N,1 serial data), with the internal clock

running at 48 MHz and 16× sampling.

Each ACE has a TXRDY and RXRDY (via MF) output that can be used to interface to a DMA controller.

2

Submit Documentation Feedback

Copyright © 2006–2008, Texas Instruments Incorporated

Product Folder Link(s): TL16C2752