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TL16C2752IFNR Folha de dados(PDF) 6 Page - Texas Instruments |
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TL16C2752IFNR Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 26 page Auto-RTS Auto-CTS Auto-RTS and Auto-CTS Functional Timing Start Byte N Start Byte N+1 Start Byte Stop Stop Stop SIN RTS RD (RD RBR) 1 2 N N+1 Start Bits 0 −7 Start Bits 0 −7 Start Bits 0 −7 Stop Stop Stop SOUT CTS TL16C2752 SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com Auto-RTS data flow control originates in the receiver timing and control block (see Figure 4) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches the defined halt trigger level 8 (see Figure 3), RTS is deasserted. The sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the defined resume trigger level is reached. The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. Figure 2. RTS Functional Timing Waveforms Figure 3. CTS Functional Timing Waveforms A. Pin numbers shown are for 44-pin PLCC FN package. Figure 4. Functional Block Diagram 6 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TL16C2752 |
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