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ACE1502VMT8 Folha de dados(PDF) 10 Page - Fairchild Semiconductor

Nome de Peças ACE1502VMT8
Descrição Electrónicos  Arithmetic Controller Engine for Low Power Applications
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
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ACE1502 Product Family Rev. 1.7
3.3 Addressing Modes
The ACEx microcontroller has seven addressing modes
indexed, indirect, direct, immediate, absolute jump, and relative
jump.
Indexed
The instruction allows an 8-bit unsigned offset value to be
added to the 11-LSBs of the X-pointer yielding a new effective
address. This mode can be used to address either data or pro-
gram memory space.
Indirect
The instruction allows the X-pointer to address any location
within the data memory space.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory space as an operand.
Immediate
The instruction contains an 8-bit immediate field as an operand.
Inherent
This instruction has no operands associated with it.
Absolute
The instruction contains an 11-bit address that directly points to
a location in the program memory space. There are two oper-
ands associated with this addressing mode. Each operand con-
tains a byte of an address. This mode is used only for the long
jump (JMP) and JSR instructions.
Relative
This mode is used for the short jump (JP) instructions where the
operand is a value relative to the current PC address. With this
instruction, software is limited to the number of bytes it can
jump, -31 or +32.
Table 8. Instruction Addressing Modes
Instruction
Immediate
Direct
Indexed
Indirect
Inherent
Relative
Absolute
ADC
ADD
AND
OR
SUBC
XOR
A, #
A, #
A, #
A, #
A, #
A, #
A, M
A, M
A, M
A, M
A, M
A, M
A, [#, X]
A, [#, X]
A, [#, X]
A, [#, X]
A, [#, X]
A, [#, X]
A, [X]
A, [X]
A, [X]
A, [X]
A, [X]
A, [X]
CLR
INC
DEC
M
M
M
A
A
A
X
X
X
IFEQ
IFGT
IFNE
IFLT
A, #
A, #
A, #
X, #
X, #
X, #
X, #
M,#
M,#
A, M
A, M
A, M
A, [#, X]
A, [#, X]
A, [#, X]
A, [X]
A, [X]
A, [X]
SC
RC
IFC
IFNC
INVC
LDC
STC
#, M
#, M
no-op
no-op
no-op
no-op
no-op
RLC
RRC
M
M
A
A
LD
ST
A, #
M, #
X, #
A, M
A, M
M, M
A, [#, X]
A, [#, X]
A, [X]
A, [X]
NOP
no-op
IFBIT
#, A
#, M
[#, X]
IFNBIT
SBIT
RBIT
#, A
#, M
#, M
#, M
[#, X]
[#, X]
[#, X]
JP
JSR
JMP
RET
RETI
INTR
[#, X]
[#, X]
no-op
no-op
no-op
Rel
M
M


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