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MC100EP445FAR2G Folha de dados(PDF) 2 Page - ON Semiconductor |
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MC100EP445FAR2G Folha de dados(HTML) 2 Page - ON Semiconductor |
2 / 19 page MC10EP445, MC100EP445 http://onsemi.com 2 Q7 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 MC10EP445 MC100EP445 Q6 Q5 VCC VCC Q4 Q3 VEE VCC SINA SINA VBB0 VEE SINB SINB SINSEL VCC CKSEL VBB1 CLK CLK CKEN RESET VCC Q2 Q1 VCC Q0 PCLK VCC PCLK Figure 1. 32−Lead LQFP Pinout (Top View) SYNC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 Figure 2. 32−Lead QFN Pinout (Top View) MC10EP445 MC100EP445 Q7 Q6 Q5 VCC VCC Q4 Q3 VEE VCC SINA SINA VBB0 VEE SINB SINB SINSEL VCC CKSEL VBB1 CLK CLK CKEN RESET VCC Q2 Q1 VCC Q0 PCLK VCC PCLK SYNC Table 1. PIN DESCRIPTION Pin SINA*, SINA* Function ECL Differential Serial Data Input A SINSEL* Q0−Q7 ECL Parallel Data Outputs ECL Serial Input Selector Pin CLK*, CLK* ECL Differential Clock Inputs PCLK, PCLK ECL Differential Parallel Clock Output SYNC* ECL Conversion Synchronizing Input CKSEL* ECL Clock Input Selector Pin VBB0, VBB1 Output Reference Voltage VCC Positive Supply VEE Negative Supply SINB*, SINB* ECL Differential Serial Data Input B CKEN* ECL Clock Enable Pin RESET* ECL Reset Pin * Pins will default logic LOW or differential logic LOW when left open. EP The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to VEE. Exposed Pad (EP) |
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Descrição semelhante - MC100EP445FAR2G |
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