MC10EP446, MC100EP446

http://onsemi.com

2

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

1234

5678

24

23

22

21

20

19

18

17

16

Figure 1. LQFP−32 Pinout (Top View)

to Power Supply to guarantee proper operation.

PCLK

PCLK

SYNC

SYNC

MC10EP446

MC100EP446

Figure 2. QFN−32 Pinout (Top View)

32

31

30

29

28

27

26

25

9

10

11

12

13

14

15

16

1

2

34

5

6

78

24

23

22

21

20

19

18

17

Exposed Pad (EP)

PCLK

PCLK

SYNC

SYNC

Table 1. PIN DESCRIPTION

PIN

FUNCTION

D0*−D7*

ECL, CMOS, or TTL Parallel Data Input

ECL Differential Serial Data Output

CLK*, CLK*

ECL Differential Clock Input

PCLK, PCLK

ECL Differential Parallel Clock Output

SYNC*, SYNC**

ECL Conversion Synchronizing Differential Input (Reset)***

CKSEL*

ECL Clock Input Selector

CKEN*, CKEN*

ECL Clock Enable Differential Input

ECL, CMOS, or TTL Input Selector

ECL Reference Mode Connection

Reference Voltage Output

Positive Supply

Negative Supply

* Pins will default LOW when left open.

**Pins will default HIGH when left open.

***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK

initiates the conversion process synchronously on the next rising edge of CLK.