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AD9122SCPZ-EP Folha de dados(PDF) 5 Page - Analog Devices |
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AD9122SCPZ-EP Folha de dados(HTML) 5 Page - Analog Devices |
5 / 12 page Enhanced Product AD9122-EP Rev. 0 | Page 5 of 12 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input V IN Logic High IOVDD = 1.8 V 1.2 V IOVDD = 2.5 V 1.6 V IOVDD = 3.3 V 2.0 V Input V IN Logic Low IOVDD = 1.8 V 0.6 V IOVDD = 2.5 V, 3.3 V 0.8 V CMOS OUTPUT LOGIC LEVEL Output V OUT Logic High IOVDD = 1.8 V 1.4 V IOVDD = 2.5 V 1.8 V IOVDD = 3.3 V 2.4 V Output V OUT Logic Low IOVDD = 1.8 V, 2.5 V, 3.3 V 0.4 V LVDS RECEIVER INPUTS1 Applies to data, DCI, and FRAME inputs Input Voltage Range, V IA or VIB 825 1675 mV Input Differential Threshold, V IDTH −100 +100 mV Input Differential Hysteresis, V IDTHH to V IDTHL 20 mV Receiver Differential Input Impedance, R IN 80 120 Ω LVDS Input Rate See Table 5 DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self-biased input, ac-coupled 1.25 V Maximum Clock Rate 1230 MHz REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V REFCLK Frequency (PLL Mode) 1 GHz ≤ f VCO ≤ 2.1 GHz 15.625 600 MHz REFCLK Frequency (SYNC Mode) See the Multichip Synchronization section of the AD9122 data sheet for conditions 0 600 MHz SERIAL PORT INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (t PWH) 12.5 ns Minimum Pulse Width Low (t PWL) 12.5 ns Setup Time, SDIO to SCLK (t DS) 2.1 ns Hold Time, SDIO to SCLK (t DH) 0.75 ns Data Valid, SDO to SCLK (t DV) 2.85 ns Setup Time, CS to SCLK (tDCSB) 1.4 ns 1 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter Value Unit LATENCY (DACCLK CYCLES) 1× Interpolation (With or Without Modulation) 64 Cycles 2× Interpolation (With or Without Modulation) 135 Cycles 4× Interpolation (With or Without Modulation) 292 Cycles 8× Interpolation (With or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles |
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