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MC100LVEL92 Folha de dados(PDF) 4 Page - ON Semiconductor

Nome de Peças MC100LVEL92
Descrição Electrónicos  5V Triple PECL Input to LVPECL Output Translator
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
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MC100LVEL92
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Table 5. AC CHARACTERISTICS (VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Toggle Frequency
TBD
TBD
TBD
GHz
tPLH
tPHL
Propagation Delay
Diff
D to Q
S.E.
490
440
590
590
690
740
510
460
610
610
710
760
530
480
630
630
730
780
ps
tSKEW
Skew
Output-to-Output (Note 2)
Part-to-Part (Diff) (Note 2)
Duty Cycle (Diff) (Note 3)
20
20
25
100
200
20
20
25
100
200
20
20
25
100
200
ps
tJITTER
Cycle-to-Cycle Jitter
TBD
TBD
TBD
ps
VPP
Input Swing (Note 4)
150
1000
150
1000
150
1000
mV
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
270
530
270
530
270
530
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. LVCC can vary 3.0 V to 3.8 V; VCC can vary 4.5 V to 5.5 V. Outputs are terminated through a 50 W resistor to LVCC − 2.0 V.
2. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
3. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
4. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈40.
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices


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