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AD5543 Folha de dados(PDF) 7 Page - Analog Devices |
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AD5543 Folha de dados(HTML) 7 Page - Analog Devices |
7 / 12 page REV. A AD5543/AD5553 –7– CIRCUIT OPERATION The AD5543/AD5553 contains a 16-/14-bit, current output, digital-to-analog converter, a serial input register, and a DAC register. Both converters use a 3-wire serial data interface. D/A Converter Section The DAC architecture uses a current steering R-2R ladder design. Figure 4 shows the typical equivalent DAC structure. The DAC contains a matching feedback resistor for use with an external op amp, (see Figure 5). With RFB and IOUT terminals connected to the op amp output and inverting node respec- tively, a precision voltage output can be achieved as: VV D AD OUT REF =× –/ , ( ) 65 536 5543 (1) VV D AD OUT REF =× –/ , ( ) 16 384 5553 (2) Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal logic to drive the DAC switches’ ON and OFF states. VREF VDD RFB IOUT RR R GND 2R 2R 2R R 5k S1 S2 DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY; SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED Figure 4. Equivalent R-2R DAC Circuit Note that a matching switch is used in series with the internal 5 k Ω feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity. VDD VREF VREF VDD U2 U1 AD5543/AD5553 –5V VO GND IOUT V+ V– RFB AD8628 Figure 5. Voltage Output Configuration These DACs are also designed to accommodate ac reference input signals. The AD5543 accommodates input reference voltages in the range of –12 V to +12 V. The reference voltage inputs exhibit a constant nominal input resistance value of 5 k Ω, ±30%. The DAC output (I OUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the AD5543 on the amplifier’s inverting input node. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. To maintain good analog perfor- mance, power supply bypassing of 0.01 µF to 0.1 µF ceramic or chip capacitors in parallel with a 1 µF tantalum capacitor is recom- mended. Due to degradation of power supply rejection ratio in frequency, users must avoid using switching power supplies. SERIAL DATA INTERFACE The AD5543/AD5553 uses a 3-wire ( CS, SDI, CLK) serial data interface. New serial data is clocked into the serial input register in a 16-bit data-word format for AD5543. The MSB is loaded first. Table II defines the 16 data-word bits. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK, subject to the data setup and hold time requirements specified in the interface timing specifications. Only the last 16 bits clocked into the serial register are inter- rogated when the CS pin is strobed to transfer the serial register data to the DAC register. Since most microcontrollers output serial data in 8-bit bytes, two data bytes can be written to the AD5543/AD5553. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register; during this strobe, the CLK should not be toggled. For the AD5553, with 16-bit clock cycles, the two LSBs are ignored. ESD Protection Circuits All logic-input pins contain back-biased ESD protection Zener diodes connected to ground (GND) and VDD as shown in Figure 6. VDD DIGITAL INPUTS 5k DGND Figure 6. Equivalent ESD Protection Circuits PCB Layout and Power Supply Bypassing It is a good practice to employ compact, minimum lead length PCB layout design. The leads to the input should be as short as possible to minimize IR drop and stray inductance. It is also essential to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capaci- tors. Low-ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple The PCB metal traces between VREF and RFB should also be matched to minimize gain error. |
Nº de peça semelhante - AD5543 |
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Descrição semelhante - AD5543 |
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