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8T74S208C-01 Folha de dados(PDF) 11 Page - Integrated Device Technology

Nome de Peças 8T74S208C-01
Descrição Electrónicos  2.5 V Differential LVDS Clock Divider and Fanout Buffer
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Fabricante Electrônico  IDT [Integrated Device Technology]
Página de início  http://www.idt.com
Logo IDT - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
August 22, 2016
8T74S208C-01 Datasheet
Applications Information
Differential Input with Built-In 50
 Termination Interface
The IN /nIN with built-in 50
 terminations accept LVDS, LVPECL,
CML and other differential signals. Both differential signals must
meet the VIN and VCMR requirements. Figure 4A to Figure 4C show
interface examples for the IN/nIN input with built-in 50
 terminations
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination
requirements.
Figure 4A. IN/nIN Input with Built-In 50
 driven by an
LVDS Driver
Figure 4B. IN/nIN Input with Built-In 50
 Driven by a CML
Driver with Open Collector
Figure 4C. IN/nIN Input with Built-In 50
 driven by an
LVPECL Driver
2.5V
LVDS
3.3V or 2.5V
50
Ω
50
Ω
IN
nIN
VT
Receiver
w ith Built-in
50
Ω
Zo = 50
Ω
Zo = 50
Ω
2.5V
2.5V
IN
nIN
VT
Receiver
with Built-in
50
Ω
Zo = 50
Ω
Zo = 50
Ω
50
Ω
50
Ω
CML – Open Collector
2.5V
LVPECL
2.5V
50
Ω
50
Ω
IN
nIN
VT
Receiver
w ith Built-in
50
Ω
Zo = 50
Ω
Zo = 50
Ω
R1
18
Ω


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