Datasheet

Datasheet

11/17

TSZ02201-0M2M0BC12020-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

18.Apr.2013 Rev.002

www.rohm.com

TSZ22111・15・001

BU24020GU

●Serial interface

Control commands are framed by a 16-bit serial input (MSB first) and are sent through CSB, SCLK, and SDATA pins.

The 4 higher-order bits specify addresses, while the remaining 12 bits specify data. Data of every bit is sent through SDATA

pin, which is retrieved during the rising edge of SCLK. Data becomes valid when CSB is Low is registered during the rising

edge of CSB. Furthermore, the interface will be synchronized with the falling edges of SCLK to output the SOUT data of the

12 bits.

＜Register map＞

Address[3:0]

Data[11:0]

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

A_Mode[1:0]

A_SEL[2:0]

A_different_output_voltage[6:0]

0

0

0

0

A_Cycle[5:0]

0

0

0

0

1

0

A_Cycle[13:6]

0

1

1

0

A_BEXC

0

0

A_BSL

A_AEXC

0

0

A_ASL

0

0

0

1

1

1

1

0

0

0

A_POS[1:0]

0

0

A_PS

A_Stop

0

0

1

0

A_EN

A_RT

A_Pulse[9:0]

0

0

1

1

A_ACT

A_BUSY

B_ACT

B_BUSY

L

L

L

L

L

L

L

L

0

1

0

0

B_Mode[1:0]

B_SEL[2:0]

B_different_output_voltage[6:0]

0

0

0

0

B_Cycle[5:0]

0

0

0

0

1

0

B_Cycle[13:6]

0

1

1

0

B_BEXC

0

0

B_BSL

B_AEXC

0

0

B_ASL

1

0

0

0

0

0

3_CHOP[1:0]

0

0

4_CHOP[1:0]

1

0

1

3_State_CTL[1:0]

3_PWM_Duty[6:0]

1

1

0

4_State_CTL[1:0]

4_PWM_Duty[6:0]

0

1

0

1

1

1

1

0

0

0

B_POS[1:0]

0

0

B_PS

B_Stop

0

1

1

0

B_EN

B_RT

B_Pulse[9:0]

0

1

1

1

A_Position[9:6]

B_Position[9:6]

L

L

L

L

1

0

1

1

0

0

0

0

0

0

Edge

0

0

0

B_CTL

A_CTL

1

1

0

0

0

0

Chopping[1:0]

CacheM

0

0

CLK_EN

CLK_DIV[3:0]

1

1

0

1

0

0

0

0

0

0

0

0

0

0

PI_CTL2 PI_CTL1

1

1

1

0

1

1

0

0

0

0

0

STB

0

0

STM_RS CMD_RS

Addresses other

than those above

Setting prohibited

(Note1) The notations A B in the register map correspond to Ach and Bch respectively. Ach is defined as 1ch and 2ch driver, Bch as 3ch and 4ch driver,

(Note2) After reset (Power ON reset), the initial condition is saved in all registers

(Note3) The addresses 4’b0011, and 4’b0111 have data (ACT, BUSY, Position [9:6]), which are internal register values and output from SOUT pin.

(Note4) For Mode, different output voltage, Cycle, EN, and RT registers, data that are written before the access to the Pulse register becomes valid and

determines the rising edge of CSB after the access to the Pulse register.

(The Mode, different output voltage, Cycle, EN, RT, and Pulse registers contain Cache registers. Any registers other than those do not contain Cache

registers.)

CSB

D13

D14

D9

D8

D10

D11

D5

D4

D6

D7

D1

D0

D2

D3

x

D15

x

D12

Address

Data

SCLK

SDATA

D9

D8

D10

D11

D5

D4

D6

D7

D1

D0

D2

D3

x

SOUT

Hiz

Hiz