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MC14013B Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC14013B Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 10 1 Publication Order Number: MC14013B/D MC14013B Dual Type D Flip-Flop The MC14013B dual type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each flip−flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip−flops for counter and toggle applications. Features • Static Operation • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge−Clocked Flip−Flop Design • Logic State is Retained Indefinitely with Clock Level either High or Low; Information is Transferred to the Output only on the Positive−going Edge of the Clock Pulse • Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range • Pin−for−Pin Replacement for CD4013B • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range − 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) − 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range − 55 to +125 °C Tstg Storage Temperature Range − 65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MARKING DIAGRAMS SOIC−14 TSSOP−14 1 14 14013BG AWLYWW 14 013B ALYW G G 1 14 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package SOEIAJ−14 1 14 MC14013B ALYWG See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION http://onsemi.com (Note: Microdot may be in either location) SOIC−14 D SUFFIX CASE 751A TSSOP−14 DT SUFFIX CASE 948G SOEIAJ−14 F SUFFIX CASE 965 11 12 13 14 8 9 10 5 4 3 2 1 7 6 RB CB QB QB VDD SB DB RA CA QA QA VSS SA DA PIN ASSIGNMENT |
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