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X1243S8I Folha de dados(PDF) 5 Page - Xicor Inc. |
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X1243S8I Folha de dados(HTML) 5 Page - Xicor Inc. |
5 / 18 page X1243 5 value to a specific day of the week is arbitrary and may be decided by the system software designer. The Clock Default values define 0=Sunday. Clock/Calendar Registers (YR, MO, DT, HR, MN, SC) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indica- tor (H21 bit) or 0 to 23 (with T24=1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (year) is 0 to 99. 24 Hour Time If the T24 bit of the HR register is 1, the RTC will use a 24-hour format. If the T24 bit is 0, the RTC will use 12- hour format and bit H21 will function as an AM/PM indi- cator with a ‘1’ representing PM. The clock defaults to Standard Time with H21=0. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The X1243 does not correct for the leap year in the year 2100. STATUS REGISTER (SR) The Status Register is located in the RTC area at address 003FH. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read an optional Low Voltage Sense bit, and read the two alarm bits. This register is logically seper- ated from both the array and the Clock/Control Regis- ters (CCR). Table 2. Status Register (SR) BAT: Battery Supply—Volatile This bit set to “1” indicates that the device is operating from VBACK, not VCC. It is a read only bit and is set/ reset by hardware. AL1, AL0: Alarm bits—Volatile These bits announce if either alarm 1 or alarm 2 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occuring during an SR read operation will remain set after the read operation is complete. RWEL: Register Write Enable Latch—Volatile This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence. WEL: Write Enable Latch—Volatile The WEL bit controls the access to the CCR and mem- ory array during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR or any array address will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part pow- ers up again. Writes to WEL bit do not cause a non-vol- atile write cycle, so the device is ready for the next operation immediately after the stop condition. RTCF: Real Time Clock Fail Bit—Volatile This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set by hardware when the device powers up after having lost all power to the device. The bit is set regardless of whether VCC or VBACK is applied first. The loss of one or the other supplies does not result in setting the RTCF bit. The first valid write to the RTC (writing one byte is sufficient) resets the RTCF bit to ‘0’. Unused Bits: These devices do not use bits 3 or 4, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations. Addr 7 6 5 4 3 2 1 0 003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF Default 0 0 0 0 0 0 0 0 |
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