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AD5531 Folha de dados(PDF) 7 Page - Analog Devices |
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AD5531 Folha de dados(HTML) 7 Page - Analog Devices |
7 / 16 page REV. 0 AD5530/AD5531 –7– TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the end- points of the DAC transfer function. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is a measure of the output error when all 0s are loaded to the DAC latch. Full-Scale Error This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF – 1 LSB. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-s and is mea- sured when the digital input code is changed by 1 LSB at the major carry transition. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V. 2 REFIN This is the voltage reference input for the DAC. Connect to external +5 V reference for specified bipolar ±10 V output. 3 LDAC Load DAC logic input (active low). When taken low, the contents of the shift register are transferred to the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising edge of SYNC. 4 SDIN Serial data input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK. 5 SYNC Active low control input. Data is clocked into the shift requester on the falling edges of SCLK. 6 RBEN Active low readback enable function. This function allows the contents of the DAC register to be read. Data from the DAC register will be shifted out on SDO pin on each rising edge of SCLK. 7 SCLK Clock input. Data is clocked into the input register on the falling edge of SCLK. 8 SDO Serial data out. This pin is used to clock out the serial data previously written to the input shift register or may be used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left high impedance. 9 CLR Level sensitive, active low input. A falling edge of CLR resets V OUT to DUTGND. The contents of the registers are untouched. 10 PD This allows the DAC to be put into a power-down state. 11 GND Ground reference 12 NC Do not connect anything to this pin. 13 VSS Negative analog supply voltage, –12 V ±10% or –15 V ±10% for specified performance. 14 DUTGND VOUT is referenced to the voltage applied to this pin. 15 VOUT DAC output 16 VDD Positive analog supply voltage, +12 V ±10% or +15 V ±10% for specified performance. |
Nº de peça semelhante - AD5531 |
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Descrição semelhante - AD5531 |
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