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AK5552VN Folha de dados(PDF) 31 Page - Asahi Kasei Microsystems |
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AK5552VN Folha de dados(HTML) 31 Page - Asahi Kasei Microsystems |
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31 / 68 page  [AK5552] 015099871-E-00 2016/03 - 31 - 12. Functional Descriptions ■ Digital Core Power Supply The digital core of the AK5552 is operates off of a 1.8 V power supply. Normally, this voltage is generated by the internal LDO from TVDD (3.3 V) for digital interface. The internal LDO will be powered up by setting the LDOE pin = “H”. Set the LDOE pin to “L” and supply a 1.8 V power to the VDD18 pin externally when a 1.8 V is used as TVDD. ■ Output Mode The AK5552 is able to output either PCM or DSD data. The DP pin or DP bit select the output mode. Set the PW2 pin = PW1 pin = PW0 pin = “L” or RSTN bit = “0” or PW2-1 bits = “00” to reset all channels when changing the PCM/DSD mode. The AK5552 outputs data from the SDTO1 pin by BICK and LRCK in PCM mode. DSD data are output from the DSDOL1 and DSDOR1 pin by DCLK in DSD mode. DP pin DP bit Interface L 0 PCM H 1 DSD Table 1. PCM/DSD Mode Control ■ Master Mode and Slave Mode The AK5552 requires a master clock (MCLK), an audio serial data clock (BICK) and an output channel clock (LRCK) in PCM mode. In this case, the LRCK frequency will be the sampling frequency. Both master and slave modes are available in PCM mode. In master mode, the AK5552 internally generates BICK and LRCK clocks from MCLK inputs and outputs them from the BICK pin and the LRCK pin. MCLK must be synchronized with BICK and LRCK but the phase is not important. The MSN pin controls master/slave mode. The AK5552 is in master mode when the MSN pin = “H” and in slave mode when the MSN pin = “L”. The AK5552 requires a master clock (MCLK) in DSD mode. Slave mode is not available in DSD mode, only master mode is supported. ■ System Clock [1] PCM Mode The external system clocks, which are required to operate the AK5552, are MCLK, BICK and LRCK in PCM mode. MCLK frequency is determined based on LRCK frequency, according to the operation mode. Table 2, Table 3 and Table 4 show MCLK frequencies correspond to the normal audio rate. Set the frequency ratio between Sampling frequency and MCLK by the CKS3-0 pins (Table 5). All channels must be reset when changing the clock mode or audio interface format by the CKS2-0 pins (bits), TDM1-0 pins (bits), DIF1-0 pins (bits) and the MSN pin. In parallel control mode, all channels will be reset by the PDN pin = “L” or PW2-0 pins = “LLL”. In serial control mode, all channels will be reset by RSTN bit = “0” or PW4-1 bits = “0H”. A stable clock must be supplied after releasing the reset. The AK5552 integrates a phase detection circuit for LRCK. If the internal timing becomes out of synchronization in slave mode, the AK5552 is reset automatically and the phase is resynchronized. The following sequence must be executed when synchronizing multiple AK5552 ’s. Stop all AK5552’s in reset status by setting the PDN pin = “L” → “H” after stopping the system clock. Make pin or register settings while all channels are in reset status. After that, input the same system clock to all AK5552 ’s. |
Nº de peça semelhante - AK5552VN_16 |
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Descrição semelhante - AK5552VN_16 |
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