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AK5556VN Folha de dados(PDF) 47 Page - Asahi Kasei Microsystems |
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AK5556VN Folha de dados(HTML) 47 Page - Asahi Kasei Microsystems |
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47 / 69 page  [AK5556] 015099857-E-00 2016/03 - 47 - ■ CH Power Down & Channel Summation Setting (PCM Mode, DSD Mode) [1] Parallel Control Mode The setting of the PW2-0 pins and the ODP pin controls the channel power-down and channel summation mode setting in parallel mode (Table 11-Table 16). The PDN pin must be set to “L” when changing the ODP pin and the PW2-0 pins. The power consumption of the device can be improved by setting unused channels to power-down state. In this case, the channel circuit that is powered down will be reset. When the ODP pin = “L”, the PW2-0 pins control channel power-down and 6-to-3 mode. In this mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1 and DSDOR1) by dividing into half amplitude. In the same manner, AIN3 and AIN4 channel data are summed digitally and output from the SDTO2 (DSDOL2 and DSDOR2) by dividing into half amplitude. AIN5 and AIN6 channel data are summed digitally and output from the SDTO3 (DSDOL3 and DSDOR3) by dividing into half amplitude. PW2 pin PW1 pin PW0 pin Power ON/OFF Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 L L L OFF OFF OFF OFF OFF OFF L L H ON OFF ON ON ON ON L H L OFF ON ON ON ON ON L H H ON ON ON ON ON ON H L L OFF OFF ON ON ON ON H L H ON OFF ON ON ON ON H H L OFF ON ON ON ON ON H H H ON ON ON ON ON ON Table 11. Channel Power ON/OFF (Parallel Control Mode, ODP pin= “L”) PW2 pin PW1 pin PW0 pin Data on Slot Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 L L L All “0” All “0” All “0” All “0” All “0” All “0” L L H CH6 All “0” (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 (CH1+2)/2 L H L All “0” CH5 (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 (CH1+2)/2 L H H (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 (CH1+2)/2 H L L All “0” All “0” CH4 CH3 CH2 CH1 H L H CH6 All “0” CH4 CH3 CH2 CH1 H H L All “0” CH5 CH4 CH3 CH2 CH1 H H H CH6 CH5 CH4 CH3 CH2 CH1 Table 12. Slot Data Assign (Parallel Control Mode, ODP pin= “L”) When the ODP pin = “H”, the AK5556 becomes optimal data placement mode and data slots can be used efficiently. The PW2-0 pins control power down, 6-to-3 mode, 4-to-1 mode and 6-to-1 mode. In 6-to-3 mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into half amplitude. In the same manner, AIN3 and AIN4 channel data are summed digitally and output from the SDTO1 (DSDOR1) of the slot2 by dividing into half amplitude. AIN5 and AIN6 channel data are summed digitally and output from the SDTO2 (DSDOL2) of the slot3 by dividing into half amplitude. In 4-to-1 mode, AIN1 - AIN4 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into quarter amplitude. AIN5 – AIN6 channel data are summed digitally and output from the SDTO1 (DSDOR1) of the slot2 by dividing into half amplitude. In 6-to-1 mode, AIN1 – AIN6 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into 1/6 amplitude. |
Nº de peça semelhante - AK5556VN_16 |
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Descrição semelhante - AK5556VN_16 |
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