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LSM6DS0 Folha de dados(PDF) 51 Page - STMicroelectronics |
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LSM6DS0 Folha de dados(HTML) 51 Page - STMicroelectronics |
51 / 59 page DocID025604 Rev 3 51/59 LSM6DS0 Register description 59 7.33 FIFO_CTRL (2Eh) FIFO control register. 7.34 FIFO_SRC (2Fh) FIFO status control register. Table 81. FIFO_SRC register Table 82. FIFO_SRC register description Table 78. FIFO_CTRL register FMODE2 FMODE1 FMODE0 FTH4 FTH3 FTH2 FTH1 FTH0 Table 79. FIFO_CTRL register description FMODE [2:0] FIFO mode selection bits. Default value: 000 For further details refer to Table 80. FTH [4:0] FIFO threshold level setting. Default value: 0 0000 Table 80. FIFO mode selection FMODE2 FMODE1 FMODE0 Mode 0 0 0 Bypass mode. FIFO turned off 0 0 1 FIFO mode. Stop collecting data when FIFO is full. 0 1 0 Reserved 0 1 1 Continuous mode until trigger is deasserted, then FIFO mode. 1 0 0 Bypass mode until trigger is deasserted, then Continuous mode. 1 1 0 Continuous mode. If the FIFO is full, the new sample over- writes the older sample. FTH OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 FTH FIFO threshold status. (0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level OVRN FIFO overrun status. (0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten) For further details refer to Table 83. FSS [5:0] Number of unread samples stored in FIFO. (000000: FIFO empty; 100000: FIFO full, 32 unread samples) For further details refer to Table 83. |
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