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TP11362A Folha de dados(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças TP11362A
Descrição Electrónicos  Quad Adaptive Differential PCM Processor
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP11362A Folha de dados(HTML) 5 Page - National Semiconductor (TI)

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Functional Description (Continued)
by a receive (decoder) operation. For the encoding opera-
tion, the PCM data is stored in the 8-bit shift register at the
falling edge of CE while TRB is high. The TP11362A pro-
cesses the data within 123 CLK periods during the following
cycle of CE. The encoded ADPCM data is loaded into the
5-bit parallel-to-serial output register with the falling edge of
CE. The MSB data is shifted out first with the leading edge of
CE, and subsequent data is shifted out with the rising edge
of ASCK. For the decoding operation, the ADPCM data is
latched and transferred to the core at the falling edge of CE
while TRB is low. The data is processed within 123 CLK pe-
riods and the decoded 8-bit PCM data is shifted out with the
MSB first.
PSCK and ASCK are the clocks for the PCM and ADPCM
data streams, respectively. They must be high during the
transition of CE. Note that PSCK and ASCK are shown as
gated clocks as an option to conserve power. PSCK and
ASCK need only be valid while CE is high.
DS012877-5
FIGURE 3. Serial Output Structure
5
www.national.com


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