RENESAS TECHNICAL UPDATE

TN-RIN-

A020A/E

Data :

Mar. 24, 2017

(c) 2017. Renesas Electronics Corporation. All rights reserved.

Page 9 of 10

No.11 3.19.1 Features

ECC error interrupt functions are added.

V4.00

V4.01

Page

Description

Page

Description

64

[3.19.1 Features]

-

Communication bus latency: 1 for read / write access

-

Fixed-priority communication bus arbitration

-

128-bit communication bus width

-

128-bit RAM bus width (without ECC)

-

Communication bus transfer size: 8/16/32/128-bit selectable

64

[3.19.1 Features]

-

Communication-bus latency: latency is 1 in read and write access

-

Arbitration of access when contention arises: Fixed priority (the communication bus is given priority)

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Communication bus width: 128 bits

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RAM bus width: 128 bits (without ECC circuit)

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Communication-bus transfer size: 8-, 16-, 32-, 128-bit transfer selectable

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ECC response: 1-bit error correction, 2-bit error detection

No.12 3.20.1 Features

Supported functions; Internal DMA, Buffer Allocator, and Header EnDec are added.

V4.00

V4.01

Page

Description

Page

Description

65

[3.20.1 Features]

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Task Scheduler



Hardware ISR : Maximum 32 selectable from 128 interrupts



Contexts : 64



Semaphores : 128



Events : 64



Mailboxes : 64



Mailbox elements : 192



Context priorities: 16

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Hardware Function Manager

65

[3.20.1 Features]

- Task Scheduler



Hardware ISR: 32 routines selectable from 128 interrupt sources



Number of contexts elements: 64



Number of semaphore identifiers: 128



Number of event identifiers: 64



Number of mailbox identifiers: 64



Number of mailbox elements: 192



Number of context priority levels: 16

- Hardware Function Manager

- Internal DMA

- Buffer allocator