Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

UPD48288118AF1 Folha de dados(PDF) 41 Page - Renesas Technology Corp

Nome de Peças UPD48288118AF1
Descrição Electrónicos  288M-BIT Low Latency DRAM
Download  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48288118AF1 Folha de dados(HTML) 41 Page - Renesas Technology Corp

Back Button UPD48288118AF1 Datasheet HTML 37Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 38Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 39Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 40Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 41Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 42Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 43Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 44Page - Renesas Technology Corp UPD48288118AF1 Datasheet HTML 45Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 52 page
background image
µµµµPD48288118AF1
R10DS0255EJ0101 Rev. 1.01
Page 41 of 51
Jan. 15, 2016
3.
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Table 3-1. Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
12A
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS
11A
Test Mode Select. This is the command input for the TAP controller state
TDI
12V
Test Data Input. This is the input side of the serial registers placed between TDI
and TDO. The register placed between TDI and TDO is determined by the state
of the TAP controller state machine and the instruction that is currently loaded in
TDO
11V
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the POWER-UP.
Table 3-2. JTAG DC Characteristics (0°C
≤≤≤≤ TC ≤≤≤≤ 95°C, 1.7 V ≤≤≤≤ VDD ≤≤≤≤ 1.9 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Notes
JTAG Input leakage
current
ILI
0 V
≤ VIN ≤ VDD
−5.0
+5.0
µA
JTAG I/O leakage current
ILO
0 V
≤ VIN ≤ VDD Q ,
−5.0
+5.0
µA
Outputs disabled
JTAG input HIGH voltage
VIH
VREF + 0.15
VDD + 0.3
V
1, 2
JTAG input LOW voltage
VIL
VSSQ
− 0.3
VREF
− 0.15
V
1, 2
JTAG output HIGH voltage
VOH1
| IOHC | = 100
µA
VDDQ
− 0.2
V
VOH2
| IOHT | = 2 mA
VDDQ
− 0.4
V
JTAG output LOW voltage
VOL1
IOLC = 100
µA
0.2
V
1
VOL2
IOLT = 2 mA
0.4
V
1
Notes 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH (AC)
≤ VDD + 0.7 V for t ≤ tCK/2.
Undershoot: VIL (AC)
≥ –0.5 V for t ≤ tCK/2.
During normal operation, VDDQ must not exceed VDD.


Nº de peça semelhante - UPD48288118AF1

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
Renesas Technology Corp
UPD48288118AFF-E18-DW1 RENESAS-UPD48288118AFF-E18-DW1 Datasheet
1Mb / 52P
   288M-BIT Low Laten cy DRAM Separate I/O
Oct 01, 2012
UPD48288118AFF-E18-DW1-A RENESAS-UPD48288118AFF-E18-DW1-A Datasheet
1Mb / 52P
   288M-BIT Low Laten cy DRAM Separate I/O
Oct 01, 2012
UPD48288118AFF-E24-DW1 RENESAS-UPD48288118AFF-E24-DW1 Datasheet
1Mb / 52P
   288M-BIT Low Laten cy DRAM Separate I/O
Oct 01, 2012
UPD48288118AFF-E24-DW1-A RENESAS-UPD48288118AFF-E24-DW1-A Datasheet
1Mb / 52P
   288M-BIT Low Laten cy DRAM Separate I/O
Oct 01, 2012
UPD48288118AFF-E25-DW1 RENESAS-UPD48288118AFF-E25-DW1 Datasheet
1Mb / 52P
   288M-BIT Low Laten cy DRAM Separate I/O
Oct 01, 2012
More results

Descrição semelhante - UPD48288118AF1

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
Renesas Technology Corp
UPD48288209AF1 RENESAS-UPD48288209AF1 Datasheet
1Mb / 54P
   288M-BIT Low Latency DRAM
UPD48288209-A RENESAS-UPD48288209-A Datasheet
862Kb / 50P
   288M-BIT Low Latency DRAM Common I/O
Feb 01, 2013
UPD48288118-A RENESAS-UPD48288118-A Datasheet
843Kb / 48P
   288M-BIT Low Latency DRAM Separate I/O
Feb 01, 2013
UPD48576118F1 RENESAS-UPD48576118F1 Datasheet
1Mb / 52P
   576M-BIT Low Latency DRAM
UPD48576209F1 RENESAS-UPD48576209F1 Datasheet
1Mb / 54P
   576M-BIT Low Latency DRAM
UPD48288209A RENESAS-UPD48288209A Datasheet
1Mb / 53P
   288M-BIT Low Laten cy DRAM Common I/O
Oct 01, 2012
UPD48288109A RENESAS-UPD48288109A Datasheet
1Mb / 52P
   288M-BIT Low Laten cy DRAM Separate I/O
Oct 01, 2012
UPD48576209 RENESAS-UPD48576209 Datasheet
1Mb / 53P
   576M-BIT Low Latency DRAM Common I/O
Oct 01, 2012
UPD48576109 RENESAS-UPD48576109 Datasheet
1Mb / 52P
   576M-BIT Low Latency DRAM Separate I/O
Oct 01, 2012
logo
Elpida Memory
EDR2518ABSE ELPIDA-EDR2518ABSE Datasheet
1Mb / 79P
   288M bits Direct Rambus DRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


Folha de dados Download

Go To PDF Page


Ligação URL




Privacy Policy
ALLDATASHEETPT.COM
ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com