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UPD48288118AF1 Folha de dados(PDF) 24 Page - Renesas Technology Corp

Nome de Peças UPD48288118AF1
Descrição Electrónicos  288M-BIT Low Latency DRAM
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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UPD48288118AF1 Folha de dados(HTML) 24 Page - Renesas Technology Corp

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µµµµPD48288118AF1
R10DS0255EJ0101 Rev. 1.01
Page 24 of 51
Jan. 15, 2016
2.11 Read Operation (READ)
Read accesses are initiated with a READ command, as shown in Figure 2-12. Row and bank addresses are provided
with the READ command.
During READ bursts, the memory device drives the read data edge-aligned with the QK signal. After a programmable
READ latency, data is available at the outputs. The data valid signal indicates that valid data will be present in the next
half clock cycle.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid
data edge considered the data generated at the Q0–Q8. tQKQ1 is the skew between QK1 and the last valid data edge
considered the data generated at the Q9–Q17. tQKQx is derived at each QKx clock edge and is not cumulative over time.
After completion of a burst, assuming no other commands have been initiated, Q will go High-Z. Back-to-back READ
commands are possible, producing a continuous flow of output data.
Minimum READ data valid window can be expressed as MIN.(tQKH, tQKL) – 2 x MAX.(tQKQx)
Any READ burst may be followed by a subsequent WRITE command. Figure 2-16. READ followed by WRITE, BL=2,
RL=4, WL=5, Configuration 1
and Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1
illustrate the timing requirements for a READ followed by a WRITE.
Figure 2-12. READ Command
Remark A : Address
BA: Bank address
CK#
CK
WE #
REF#
CS#
ADDRESS
BANK
ADDRESS
Don't care
A
BA


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