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UPD48576209F1 Folha de dados(PDF) 43 Page - Renesas Technology Corp |
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UPD48576209F1 Folha de dados(HTML) 43 Page - Renesas Technology Corp |
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43 / 54 page  µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1 R10DS0256EJ0101 Rev. 1.01 Page 43 of 53 Jan. 15, 2016 3. JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Table 3-1. Test Access Port (TAP) Pins Pin name Pin assignments Description TCK 12A Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 11A Test Mode Select. This is the command input for the TAP controller state TDI 12V Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in TDO 11V Test Data Output. This is the output side of the serial registers placed between TDI and TDO. Output changes in response to the falling edge of TCK. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH for five rising edges of TCK. The TAP controller state is also reset on the POWER-UP. Table 3-2. JTAG DC Characteristics (0°C ≤≤≤≤ TC ≤≤≤≤ 95°C, 1.7 V ≤≤≤≤ VDD ≤≤≤≤ 1.9 V, unless otherwise noted) Parameter Symbol Conditions MIN. MAX. Unit Notes JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD −5.0 +5.0 µA JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDD Q , −5.0 +5.0 µA Outputs disabled JTAG input HIGH voltage VIH VREF + 0.15 VDD + 0.3 V 1, 2 JTAG input LOW voltage VIL VSSQ − 0.3 VREF − 0.15 V 1, 2 JTAG output HIGH voltage VOH1 | IOHC | = 100 µA VDDQ − 0.2 V VOH2 | IOHT | = 2 mA VDDQ − 0.4 V JTAG output LOW voltage VOL1 IOLC = 100 µA 0.2 V 1 VOL2 IOLT = 2 mA 0.4 V 1 Notes 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ tCK/2. Undershoot: VIL (AC) ≥ –0.5 V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. |
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