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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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HT48R063B Folha de dados(PDF) 42 Page - Holtek Semiconductor Inc |
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HT48R063B Folha de dados(HTML) 42 Page - Holtek Semiconductor Inc |
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42 / 82 page  HT48R063B/064B/065B/066B Rev. 1.20 42 June 3, 2013 Timer Mode In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal inter- rupt signal each time the Timer/Event Counter over- flows. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Regis- ter must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Timer Mode Bit7 Bit6 10 In this mode the internal clock is used as the timer clock. The timer input clock source is either fSYS ,fSYS/4 or the LXT oscillator. However, this timer clock source is fur- ther divided by a prescaler, the value of which is deter- mined by the bits TnPSC2~TnPSC0 in the Timer Control Register. The timer-on bit, TnON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value al- ready loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, how- ever, the internal interrupts can be disabled by ensuring that the ETnI bits of the INTCn register are reset to zero. Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer TCn pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode Bit7 Bit6 01 In this mode, the external timer TCn pin, is used as the Timer/Event Counter clock source, however it is not di- vided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit, TnE, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the TnEG is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Coun- ter will reload the value already loaded into the preload register and continue counting. The interrupt can be dis- abled by ensuring that the Timer/Event Counter Inter- rupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. As the external timer pin is shared with an I/O pin, to en- sure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Idle/Sleep Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input TCn pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. I n c r e m e n t T i m e r C o n t r o l l e r P r e s c a l e r O u t p u t T i m e r + 1 T i m e r + 2 T i m e r + N T i m e r + N + 1 Timer Mode Timing Chart T i m e r + 2 E x t e r n a l E v e n t I n c r e m e n t T i m e r C o u n t e r T i m e r + 3 T i m e r + 1 Event Counter Mode Timing Chart (TnEG=1) |
Nº de peça semelhante - HT48R063B_13 |
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Descrição semelhante - HT48R063B_13 |
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