SN65MLVD201, SN65MLVD203

SN65MLVD206, SN65MLVD207

SLLS558A – DECEMBER 2002 – JUNE 2003

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11

tc(n)

1/f0

Period Jitter

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

CLOCK INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

tjit(per)=tc(n)–1/f0

tjit(pp)

VA –VB

INPUTS

VA –VB

0.2 V – Type 1

0.4 V – Type 2

VIC

1 V

VOH

VCC/2

VOL

VOH

VOL

VCC/2

VOH

VOL

VCC/2

VA

VB

NOTES:A. All input pulses are supplied by an Agilent 8304A Stimulus System.

B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C. Period jitter is measured using a 100 MHz 50

±1% duty cycle clock input.

D. Peak-to-peak jitter is measured using a 200 Mbps 215–1 PRBS input.

Figure 12. Receiver Jitter Measurement Waveforms

PIN ASSIGNMENTS

SN65MLVD203D (Marked as MLVD203)

SN65MLVD207D (Marked as MLVD207)

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC

R

RE

DE

D

GND

GND

A

B

Z

Y

NC

NC – No internal connection

1

2

3

4

8

7

6

5

R

RE

DE

D

B

A

GND

SN65MLVD201D (Marked as MF201)

SN65MLVD206D (Marked as MF206)

(TOP VIEW)