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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ACEX1 Folha de dados(PDF) 4 Page - List of Unclassifed Manufacturers |
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ACEX1 Folha de dados(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 86 page  4 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet General Description Altera® ACEX 1K devices provide a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. These elements make ACEX 1K suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications. Based on reconfigurable CMOS SRAM elements, the ACEX 1K architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components. The advanced process and the low voltage requirement of the 2.5-V core allow ACEX 1K devices to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches. The ability to reconfigure ACEX 1K devices enables complete testing prior to shipment and allows the designer to focus on simulation and design verification. ACEX 1K device reconfigurability eliminates inventory management for gate array designs and test vector generation for fault coverage. Table 4 shows ACEX 1K device performance for some common designs. All performance results were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Notes: (1) This application uses combinatorial inputs and outputs. (2) This application uses registered inputs and outputs. Table 4. ACEX 1K Device Performance Application Resources Used Performance LEs EABs Speed Grade Units -1 -2 -3 16-bit loadable counter 16 0 285 232 185 MHz 16-bit accumulator 16 0 285 232 185 MHz 16-to-1 multiplexer (1) 10 0 3.5 4.5 6.6 ns 16-bit multiplier with 3-stage pipeline(2) 592 0 156 131 93 MHz 256 × 16 RAM read cycle speed (2) 0 1 278 196 143 MHz 256 × 16 RAM write cycle speed (2) 0 1 185 143 111 MHz |
Nº de peça semelhante - ACEX1 |
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Descrição semelhante - ACEX1 |
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