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AD5242BRU100-REEL7 Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças AD5242BRU100-REEL7
Descrição Electrónicos  I2C Compatible 256-Position Digital Potentiometers
Download  16 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD5242BRU100-REEL7 Folha de dados(HTML) 6 Page - Analog Devices

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REV. B
AD5241/AD5242
–6–
t8
t1
t8
t3
t2
t2
t9
t5
t10
S
P
t7
t4
S
P
SDA
SCL
t6
Figure 1. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I
2C bus in the following serial format:
S0
1
0
11
AD1 AD0 R/
W
A
A/B RS
SD
O1
O2
XXX
A
D7
D6
D5
D4
D3D2
D1D0
A
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
where:
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.
R/
W = Read Enable at High and output to SDA. Write Enable at Low.
A/B = RDAC subaddress select. ‘0’ for RDAC1 and ‘1’ for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as
SHDN except inverse logic.
O1, O2 = Output logic pin latched values.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
1
91
1
99
0
1
0
1
1AD1
AD0
R/
W
A/B
RS
SD
O1
O2
X
X
X
D7
D6
D5
D4D3D2
D1
D0
ACK BY
AD5241
ACK BY
AD5241
ACK BY
AD5241
STOP BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
SCL
SDA
Figure 2. Writing to the RDAC Serial Register
1
91
9
0
1
0
1
1AD1
AD0
R/
W
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5241
NO ACK BY
MASTER
STOP BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED
RDAC REGISTER IN WRITE MODE
SCL
SDA
Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode


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