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GS7025-CQM Folha de dados(PDF) 10 Page - Gennum Corporation |
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GS7025-CQM Folha de dados(HTML) 10 Page - Gennum Corporation |
10 / 13 page GENNUM CORPORATION 522 - 80 - 00 10 3. FREQUENCY ACQUISITION The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock, the GS7025 uses a frequency acquisition circuit. The frequency acquisition circuit sweeps the VCO control voltage so that the VCO frequency changes from -10% to +10% of the centre frequency. Figure 11 shows a typical sweep waveform. Fig. 11 Typical Sweep Waveform The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, ΙCP: The nominal sweep time is approximately 121µs when CLF1 = 15nF and ΙCP = 165µA (RVCO = 365Ω). An internal system clock determines tsys (see section 3-1, Logic Circuit). 3-1. Logic Circuit The GS7025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL.The period of the system clock is set by the COSC capacitor and is: The recommended value for tsys is 450µs (COSC = 4.7nF) 4. LOCKING The GS7025 indicates valid lock when the following three conditions are satisfied: 1. Input data is detected. 2. The incoming data signal and the PLL clock are phase locked. 3. The system is not locked to an integer-multiple harmonic of a 270Mb/s SMPTE 259M-C signal. The GS7025 defines the presence of input data when at least one data transition occurs every 1µs. The GS7025 assumes that it is NOT locked to a harmonic if the pattern ‘101’ or ‘010’ (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150µs. In a harmonically locked system, all bit cells are double clocked and the above patterns become ‘110011’ and ‘001100’, respectively. 4-1. Lock Time Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). When input data to the GS7025 is removed, the GS7025 latches the current state. Therefore, when data is reapplied, the GS7025 begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS7025 locks very quickly. The nominal lock time depends on the switching time and is summarized in the Table 3. To acquire lock, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. Maximum lock time is 2Tcycle + 2tsys. The nominal value of Tcycle for the GS7025 operating in a typical SMPTE 259M-C application is approximately 1.3ms. The GS7025 has a dedicated LOCK output (pin 39) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5µs, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted. VLF tswp Tcycle Tcycle = tswp + tsys tsys A t SWP 4C LF1 3I CP ---------------- = t sys 9.6 10 4 C OSC onds sec [] × × = TABLE 3. SWITCHING TIME LOCK TIME <0.5µs 10µs 0.5µs - 10ms 2tsys >10ms 2Tcycle + 2tsys |
Nº de peça semelhante - GS7025-CQM |
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Descrição semelhante - GS7025-CQM |
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