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AD5557 Folha de dados(PDF) 4 Page - Analog Devices

Nome de Peças AD5557
Descrição Electrónicos  Dual Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD5557 Folha de dados(HTML) 4 Page - Analog Devices

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AD5547/AD5557
Rev. 0 | Page 4 of 20
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AC CHARACTERISTICS4
Output Voltage Settling Time
tS
To ±0.1% of full scale, data cycles from zero scale
to full scale to zero scale
0.5
µs
Reference Multiplying BW
BW
VREF = 5 V p-p, data = full scale
4
MHz
DAC Glitch Impulse
Q
VREF = 0 V, midscale to midscale – 1
7
nV-s
Multiplying Feedthrough Error
VOUT/VREF
VREF = 100 mV rms, f = 10 kHz
–65
dB
Digital Feedthrough
QD
WR = 1, LDAC toggles at 1 MHz
7
nV-s
Total Harmonic Distortion
THD
VREF = 5 V p-p, data = full scale, f = 1 kHz
–85
dB
Output Noise Density
eN
f = 1 kHz, BW = 1 Hz
12
nV/√Hz
Analog Crosstalk
CAT
Signal input at Channel A and measure the output
at Channel B, f = 1 kHz
–95
dB
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-V converter amplifier. The device RFB terminal is tied
to the amplifier output. The OP97’s +IN pin is grounded, and the DAC’s IOUT is tied to the OP97’s –IN pin. Typical values represent average readings measured at 25°C.
2 Guaranteed by design; not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V), and are timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD841 I-V converter amplifier.
tWR
tDS
tDH
tLWD
tLDAC
tRS
WR
DATA
LDAC
RS
Figure 3. AD5547/AD5557 Timing Diagram


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