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AD7147A Folha de dados(PDF) 17 Page - Analog Devices |
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AD7147A Folha de dados(HTML) 17 Page - Analog Devices |
17 / 69 page AD7147A Rev. B | Page 16 of 68 CDC CONVERSION SEQUENCE TIME Table 10. CDC Conversion Times for Full Power Mode SEQUENCE_STAGE_NUM Conversion Time (ms) Decimation = 64 Decimation = 128 Decimation = 256 0 0.768 1.536 3.072 1 1.536 3.072 6.144 2 2.304 4.608 9.216 3 3.072 6.144 12.288 4 3.84 7.68 15.36 5 4.608 9.216 18.432 6 5.376 10.752 21.504 7 6.144 12.288 24.576 8 6.912 13.824 27.648 9 7.68 15.36 30.72 10 8.448 16.896 33.792 11 9.216 18.432 36.864 The time required for the CDC to complete the measurement of all 12 stages is defined as the CDC conversion sequence time. The SEQUENCE_STAGE_NUM and DECIMATION bits determine the conversion time, as listed in Table 10. For example, if the device is operated with a decimation rate of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms. Full Power Mode CDC Conversion Sequence Time The full power mode CDC conversion sequence time for all 12 stages is set by configuring the SEQUENCE_STAGE_NUM and DECIMATION bits as outlined in Table 10. Figure 26 shows a simplified timing diagram of the full power mode CDC conversion time. The full power mode CDC con- version time (tCONV_FP) is set using the values shown in Table 10. CONVERSION SEQUENCE N CONVERSION SEQUENCE N + 1 CONVERSION SEQUENCE N + 2 CDC CONVERSION tCONV_FP Figure 26. Full Power Mode CDC Conversion Sequence Time Low Power Mode CDC Conversion Sequence Time with Delay The frequency of each CDC conversion while operating in the low power automatic wake-up mode is controlled by using the LP_CONV_DELAY Bits[3:2] located at Address 0x000 in addi- tion to the registers listed in Table 10. This feature provides some flexibility for optimizing the trade-off between the conversion time needed to meet system requirements and the power consumption of the AD7147A. For example, maximum power savings is achieved when the LP_CONV_DELAY bits are set to 11. With a setting of 11, the AD7147A automatically wakes up, performing a conversion every 800 ms. Table 11. LP_CONV_DELAY Settings LP_CONV_DELAY Bits Delay Between Conversions (ms) 00 200 01 400 10 600 11 800 Figure 27 shows a simplified timing example of the low power mode CDC conversion time. As shown, the low power mode CDC conversion time is set by tCONV_FP and the LP_CONV_DELAY bits. CONVERSION SEQUENCE N CONVERSION SEQUENCE N + 1 CDC CONVERSION LP_CONV_DELAY tCONV_LP tCONV_FP Figure 27. Low Power Mode CDC Conversion Sequence Time CDC CONVERSION RESULTS Certain high resolution sensors require the host to read back the CDC conversion results for processing. The registers required for host processing are located in Bank 3. The host processes the data read back from these registers using a software algorithm to determine position information. In addition to the results registers in Bank 3, the AD7147A provides the 16-bit CDC output data directly, starting at Address 0x00B of Bank 1. Reading back the CDC 16-bit conversion data register allows for customer-specific application data processing. |
Nº de peça semelhante - AD7147A |
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Descrição semelhante - AD7147A |
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