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AD7747 Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças AD7747
Descrição Electrónicos  24-Bit Capacitance-to-Digital Converter
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD7747 Folha de dados(HTML) 6 Page - Analog Devices

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AD7747
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SERIAL INTERFACE1, 2
See Figure 2
SCL Frequency
0
400
kHz
SCL High Pulse Width, tHIGH
0.6
μs
SCL Low Pulse Width, tLOW
1.3
μs
SCL, SDA Rise Time, tR
0.3
μs
SCL, SDA Fall Time, tF
0.3
μs
Hold Time (Start Condition), tHD;STA
0.6
μs
After this period, the first clock is generated
Setup Time (Start Condition), tSU;STA
0.6
μs
Relevant for repeated start condition
Data Setup Time, tSU;DAT
0.1
μs
Setup Time (Stop Condition), tSU;STO
0.6
μs
Data Hold Time, tHD;DAT (Master)
0
μs
Bus-Free Time (Between Stop and Start Condition, tBUF)
1.3
μs
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
SCL
SDA
PS
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
S
tSU;STA
tHD;STA
tSU;STO
P
tBUF
Figure 2. Serial Interface Timing Diagram


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