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MT9V023 Folha de dados(PDF) 36 Page - ON Semiconductor |
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MT9V023 Folha de dados(HTML) 36 Page - ON Semiconductor |
36 / 43 page MT9V023 www.onsemi.com 36 Propagation Delays for FRAME_VALID and LINE_VALID Signals The LV and FV signals change on the same rising master clock edge as the data output. The LV goes HIGH on the same rising master clock edge as the output of the first valid pixel’s data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel’s data. As shown in the “Output Data Timing”, FV goes HIGH 143 pixel clocks before the first LV goes HIGH. It returns LOW 23 pixel clocks after the last LV goes LOW. Figure 37. Propagation Delays for FRAME_VALID and LINE_VALID Signals PIXCLK FRAME_VALID LINE_VALID t PFLF t PFLR PIXCLK FRAME_VALID LINE_VALID Two-Wire Serial Bus Timing Detailed timing waveforms and parameters for the two-wire serial interface bus are shown in Figure 38 and Table 19. Figure 38. Two-wire Serial Bus Timing SCLK SDATA SCLK SDATA Read Start Write Start ACK ACK Stop tr_clk tf_clk tr_sdat tf_sdat 90% 10% 10% tSRTH tSCLK t SCHW t SDSW tASR tAHR tSTPS tSTPH Register Value Bit 0 Register Address Bit 7 Register Value Bit 0 Register Value Bit 7 Write Address Bit 7 Write Address Bit 0 Read Address Bit 7 Read Address Bit 0 tASW tAHW tSHDR tSDSR 90% |
Nº de peça semelhante - MT9V023_17 |
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Descrição semelhante - MT9V023_17 |
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