MRF89XA datasheet(57/140 Pages) MICROCHIP

Nome de Peças	MRF89XA

Descrição Electrónicos	Ultra Low-Power, Integrated ISM BandSub-GHz Transceiver

Download	140 Pages

Scroll/Zoom	100%

Fabricante Electrônico	MICROCHIP [Microchip Technology]

Página de início	http://www.microchip.com

Logo

57 / 140 page

 2010-2017 Microchip Technology Inc.

Preliminary

DS70000622D-page 57

MRF89XA

3.2

Frequency Synthesis Description

3.2.1

REFERENCE OSCILLATOR

The crystal oscillator (XTAL) forms the reference

oscillator of an Integer-N PLL. The crystal reference

frequency and the software controlled dividers R, P,

and S determine the output frequency of the PLL. The

guidelines for selecting the appropriate crystal with

specifications are explained in Section 4.7, Crystal

Specification and Selection Guidelines.

3.2.2

BUFFERED CLOCK OUTPUT

The buffered clock output is a signal derived from fxtal.

It can be used as a reference clock (or a sub-multiple

of it) for the host microcontroller and is an output on the

CLKOUT pin (pin 19). The pin is activated using the

CLKOCNTRL bit (CLKOUTREG<7>). The output

frequency (CLKOUT) division ratio is programmed

through the Clock Out Frequency bits (CLKOFREQ5-

CLK0FREQ1) in the Clock Output Control Register

(CLKOUTREG<6:2>). The two uses of the CLKOUT

output are:

• To provide a clock output for a host microcontroller,

thus saving the cost of an additional oscillator.

CLKOUT can be made available in any operation

mode, except Sleep mode, and is automatically

enabled at power-up.

• To provide an oscillator reference output.

Measurement of the CLKOUT signal enables

simple software trimming of the initial crystal

tolerance.

3.2.3

CLOCK REGISTERS

The registers associated with the Clock and its control

are:

• GCONREG (Register 2-1)

• CLKOUTREG (Register 2-28)

3.2.4

PHASE-LOCKED LOOP (PLL)

The frequency synthesizer of the MRF89XA is a fully

integrated integer-N type PLL. The PLL circuit requires

only five external components for the PLL loop filter

and the VCO tank circuit.

3.2.4.1

PLL Requirements

With integer-N PLL architecture, the following

conditions must be met to ensure correct operation:

• The comparison frequency, FCOMP, of the Phase

Frequency Detector (PFD) input must remain

higher than six times the PLL bandwidth (PLLBW)

to guarantee loop stability and to reject harmonics

of the comparison frequency FCOMP. This is

expressed in the inequality:

FCOMP ≥ 6 * PLLBW

• However, the PLLBW must be sufficiently high to

allow adequate PLL lock times.

• Because the divider ratio R determines FCOMP, it

should be set close to 119, leading to

FCOMP ≈ 100 kHz, which will ensure suitable PLL

stability and speed.

The following criteria govern the R, P, and S values for

the PLL block:

•64 ≤ R ≤ 169

•P+1 > S

• PLLBW = 15 kHz nominal

• Start-up times and reference frequency drives as

specified

3.2.4.2

PLL Lock Detection Indicator

The MRF89XA features a PLL lock detect indicator.

This is useful for optimizing power consumption, by

adjusting the frequency synthesizer wake-up time

(TSFS). For more information on TSFS, refer to

Table 5-4. The lock status is available by reading the

Lock Status of PLL bit (LSTSPLL) in the FIFO

Transmit

PLL

and

RSSI

Interrupt

Request

Configuration register (FTPRIREG<1>), and must be

cleared by writing a ‘1’ to this same register. The

lock status can also be seen on the PLOCK pin (pin

23) of the device by setting the LENPLL bit

(FTPRIREG<0>).

3.2.5

PLL REGISTERS

The registers associated with the PLL are:

• GCONREG (Register 2-1)

• FTPRIREG (Register 2-15)

3.2.6

SW SETTINGS OF THE VCO

To guarantee the optimum operation of the VCO over

the MRF89XA’s frequency and temperature ranges,

the settings listed in Table 3-1 should be programmed

into the MRF89XA.

Note:

Use the recommended values provided in

the Bill Of Materials (BOM) in Section 4.8,

Bill of Materials for any PLL prototype

design.

Note:

CLKOUT is disabled when the MRF89XA

is in Sleep mode. If Sleep mode is used,

the host microcontroller must have provi-

sions to run from its own clock source.

Note:

The LSTSPLL bit latches high each time

the PLL locks and must be reset by writing

a ‘1’ to LSTSPLL from FTPRIREG.

Nº de peça semelhante - MRF89XA

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
Microchip Technology	MRF89XAM8A	682Kb / 34P	868 MHz Ultra-Low Power 08/04/10
	MRF89XAM8A-I	2Mb / 140P	Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver 08/02/11
	MRF89XAM8A-I/RM	682Kb / 34P	868 MHz Ultra-Low Power 08/04/10
	MRF89XAM8AT-I/RM	682Kb / 34P	868 MHz Ultra-Low Power 08/04/10
	MRF89XAM9A	623Kb / 36P	915 MHz Ultra Low-Power Sub-GHz Transceiver Module 11/29/12

More results

Descrição semelhante - MRF89XA

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
Microchip Technology	MRF89XAM8A-I	2Mb / 140P	Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver 08/02/11
Freescale Semiconductor...	MC13191	340Kb / 24P	2.4 GHz ISM Band Low Power Transceiver
	MC13191	289Kb / 24P	2.4 GHz ISM Band Low Power Transceiver
	MC13191	373Kb / 24P	2.4 GHz ISM Band Low Power Transceiver
ATMEL Corporation	ATR2406	1Mb / 26P	Low-IF 2.4-GHz ISM Transceiver
	ATR2406	813Kb / 25P	Low-IF 2.4-GHz ISM Transceiver
	ATR2406	682Kb / 20P	LOW IF .4 GHZ ISM TRANSCEIVER
	ATR2406	850Kb / 25P	Low-IF 2.4-GHz ISM Transceiver
Semtech Corporation	SX1211	1Mb / 92P	Ultra-Low Power Integrated UHF Transceiver
List of Unclassifed Man...	RF63	3Mb / 91P	Ultra-Low Power Integrated UHF Transceiver

More results

MRF89XA Folha de dados(PDF) 57 Page - Microchip Technology

MRF89XA Folha de dados(HTML) 57 Page - Microchip Technology

Nº de peça semelhante - MRF89XA

Descrição semelhante - MRF89XA

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL