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CAT24WC257WTE13 Folha de dados(PDF) 4 Page - Catalyst Semiconductor

Nome de Peças CAT24WC257WTE13
Descrição Electrónicos  256K-Bit I2C Serial CMOS EEPROM
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Fabricante Electrônico  CATALYST [Catalyst Semiconductor]
Página de início  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

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CAT24WC257
4
Doc. No. 1030, Rev. E
FUNCTIONAL DESCRIPTION
The CAT24WC257 supports the I2C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC257
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the top
1/4 array of memory (locations 6000H to 7FFFH) is write
protected. When left floating, memory is unprotected.
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
A0, A1: Device Address Inputs
These pins are hardwired or left connected. When
hardwired, up to four CAT24WC257's may be addressed
on a single bus system. When the pins are left uncon-
nected, the default values are zero.
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
START BIT
SDA
STOP BIT
SCL
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA


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