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SLG46169 Folha de dados(PDF) 95 Page - Dialog Semiconductor

Nome de Peças SLG46169
Descrição Electrónicos  GreenPAK Programmable Mixed-signal Matrix
Download  102 Pages
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Fabricante Electrônico  DIALOG [Dialog Semiconductor]
Página de início  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46169 Folha de dados(HTML) 95 Page - Dialog Semiconductor

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Page 94 of 101
SLG46169
reg<945:944>
PIN13 pull up/down resistor value selection
00: Floating
01: 10K
10: 100K
11: 1M
reg<946>
PIN13 pull up/down resistor select
0: pull down resistor enable
1: pull up resistor enable
reg<949:947>
PIN14 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Open Drain NMOS
reg<951:950>
PIN14 pull up/down resistor value selection
00: Floating
01: 10K
10: 100K
11: 1M
reg<952>
PIN14 pull up/down resistor select
0: pull down resistor enable
1: pull up resistor enable
reg<953>
PIN14 driver strength selection
0: 1X
1: 2X
reg<961:954>
LUT3_9 data
reg<962>
Filter_1 output polarity select
0: Filter_1 output
1: Filter_1 output inverted
reg<963>
LUT3_8 or pipe delay output select
0: LUT3_8
1: 1pipe delay output
reg<964>
Pipe delay OUT1 polarity select bit
0: non-inverted
1: inverted
reg<966:965>
Delay value select for programmable delay & edge de-
tector
(VDD = 3.3V, typical condition)
00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
reg<968:967>
Select the edge mode of programmable delay & edge
detector
00: rising edge detector
01: falling edge detector
10: both edge detector
11: both edge delay
reg<969>
Select edge detector output mode
0: edge detector output
1: delayed edge detector output
reg<977:970>
8-bit pattern id
reg<978>
GPIO quick charge enable
0: Disable
1: Enable
reg<979>
NVM data read disable
0: Disable (program data can be read)
1: Enable (Program data cannot be read)
reg<980>
NVM power down
0: None (or programming enable)
1: Power Down (or programming disable)
reg<981>
Force bandgap on
0: Auto-mode
1: Enable
reg<982>
VREF Output Active Buffer Control
0: Disabled (bypass Active Buffer)
1: Enabled
reg<983>
Reserved
reg<991:984>
Reserved
Register Bit
Address
Signal Function
Register Bit Definition


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