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74LVC1G86 Folha de dados(PDF) 4 Page - NXP Semiconductors |
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74LVC1G86 Folha de dados(HTML) 4 Page - NXP Semiconductors |
4 / 12 page 2001 Apr 06 4 Philips Semiconductors Preliminary specification 2-input EXCLUSIVE-OR gate 74LVC1G86 handbook, halfpage 1 2 = 1 4 MNA039 Fig.3 IEE/IEC logic symbol. handbook, halfpage MNA040 Y B A Fig.4 Logic diagram. RECOMMENDED OPERATING CONDITIONS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 3. Above 55 °C the value of PD derates linearly with 2.5 mW/K. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V Tamb operating ambient temperature −40 +85 °C tr, tf input rise and fall times VCC = 1.65 to 2.7 V 0 20 ns/V VCC = 2.7 to 5.5 V 0 10 ns/V SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +6.5 V IIK input diode current VI <0 −−50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO >VCC or VO <0 −±50 mA VO output voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V Power-down mode; notes 1 and 2 −0.5 +6.5 V IO output source or sink current VO =0toVCC −±50 mA ICC, IGND VCC or GND current −±100 mA Tstg storage temperature −65 +150 °C PD power dissipation per package for temperature range from −40 to +85 °C; note 3 − 200 mW |
Nº de peça semelhante - 74LVC1G86 |
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Descrição semelhante - 74LVC1G86 |
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