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ML12009EP Folha de dados(PDF) 4 Page - LANSDALE Semiconductor Inc.

Nome de Peças ML12009EP
Descrição Electrónicos  MECL PLL Components Dual Modulus Prescaler
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Fabricante Electrônico  LANSDALE [LANSDALE Semiconductor Inc.]
Página de início  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

ML12009EP Folha de dados(HTML) 4 Page - LANSDALE Semiconductor Inc.

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Issue A
LANSDALE Semiconductor, Inc.
ML12009, ML12011
ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.)
Test Limits
Pin
Under
–30°C
25°C
85°C
Characteristic
Symbol
Under
Test
Min
Max
Min
Max
Min
Max
Unit
Power Supply Drain Current
ICC1
8
–88
–80
–80
mAdc
ICC2
6
5.2
5.2
5.2
mAdc
Input Current
IinH1
15
11
12
13
375
375
375
375
250
250
250
250
250
250
250
250
µAdc
IinH2
4
5
1.7
1.7
6.0
6.0
2.0
2.0
6.0
6.0
2.0
2.0
6.4
6.4
mAdc
IinH3
5
0.7
3.0
1.0
3.0
1.0
3.6
IinH4
9
10
100
100
100
100
100
100
µAdc
Leakage Current
IinL1
15
11
12
13
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
µAdc
IinL2
9
10
–1.6
–1.6
–1.6
–1.6
–1.6
–1.6
mAdc
Reference Voltage
VBB
14
–1.360
–1.160
Vdc
Logic ‘1’ Output Voltage
VOH1
(Note 1)
2
3
–1.100
–1.100
–0.890
–0.890
–1.000
–1.000
–0.810
–0.810
–0.930
–0.930
–0.700
–0.700
Vdc
VOH2
7
–2.8
–2.6
–2.4
Logic ‘0’ Output Voltage
VOL1
(Note 1)
2
3
–1.990
–1.990
–1.675
–1.675
–1.950
–1.950
–1.650
–1.650
–1.925
–1.925
–1.615
–1.615
Vdc
VOL2
7
–4.26
–4.40
–4.48
Logic ‘1’ Threshold Voltage
VOHA
(Note 2)
2
3
–1.120
–1.120
–1.020
–1.020
–0.950
–0.950
Vdc
Logic ‘0’ Threshold Voltage
VOLA
(Note 3)
2
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Short Circuit Current
IOS
7
–65
–20
–65
–20
–65
–20
mAdc
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
VIHmax
VILmin
Clock Input


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